T3 Violation in DFT

Pattern are generated on the DFT logic inserted design, before generating the pattern the tool will check for certain rules and reports DRC violations as a part of ATPG flow. One of the rule is Tracing of scan chains from output pin to scan input pin, if the tool is unable to trace back, it will through a Trace (T rule) violation.

When the shift procedure failed to create a path from scan chain output pin back to scan chain input pin, then tool reports a trace violation (T-3). In this case engineer as to take care to properly constrain the input pins which are responsible for activating the DFT logic in the design. T3 violation can occur due to many reasons, few of them are explained below

Case I:

In this case as shown below after tracing till 10^th scan cell, chain tracing was blocked due the BLACK BOX present in the scan chain path and reports T3 violation by tool.

This can be solved by loading the BLACK BOX definition during the setup phase, which will help the tool to trace the chain from scan_out pin to scan_in pin  

Case II:

In this case shown below, there is a trace blockage in scan chain at 2^nd cell as there is no toggling activity of clock. When we trace back the clock pin, we can see that clock is coming from a mux and select line for mux is x.

This can be solved by making clock of FF3 to toggle, which makes the input D to appear at output pin of FF3. This makes the select line to low (i.e. is 0) and the D0 pin will be selected, which is toggling.

We have to make the clk1 pin to toggle, constraint the D pin of FF3 to 1 and we need to inform the tool about the constraints by following commands in a do file.
add_clock 0 clk1
add_input_constraint D –c0

We also need to modify the test procedure to pulse the clk1.
Template gen_tp =
offstate “clk1” 0 ;
force_pi 0 ;
 measure_po  100 ;
pulse clk1 200 100 ;
period 400 ;
end;

procedure test_setup =
temeplate gen_tp ;
cycle =
force D 0 ;
pulse clk1 ;
end ;
end;

CHISEL

Chisel (Constructing Hardware in a Scala Embedded Language)

Is a new hardware language which made open source by UC Berkeley. Chisel supports the advance hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel provides the flexibility of concepts like object orientation, functional programming, parameterized types and type inference over the VHDL or Verilog hardware languages. Chisel adds hardware construction primitives to the scala programming language, providing designers with power of a modern programming language to write complex, prameterizable circuit generators that produce sythesizble Verilog. With single chisel code, we can generate a high-speed C++ based cycle –accurate software simulator, or low-level Verilog design for ASIC or FPGA for synthesis, place and route.

Chisel is powered by FIRRTL (highly parameterized generators and layered domain-specific hardware languages), a hardware complier that performs optimization of chisel-generated circuits.
Steps involved to generate the Verilog from chisel code

1. The Chisel stage/Font-end compiles chisel to a circuit intermediate representation called FIRRTL(highly parameterized generators and layered domain-specific hardware languages
2. FIRRTL stage/ mid-end then optimizes FIRRTL and then applies user custom transformations
3. Finally the Verilog stage/Backend generated the Verilog based on the optimized FIRRTL.

Utilisation Factor

Utilization factor gives us information how much area must be occupied by the standard cell. As we increase the utilization factor , total area of the chip or block will be decreased. Let us discuss how the total area decreases and total area was

Total Core Area = area occupied by macros+area occupied by standard cell+ empty area

UF  is defined as (area occupied by the standard cell)/(Total Core Are) and the UF is varied from .3 to .8 . In  industry mostly they will go with utilization factor of 0.7 -0.8

Assume that standard cell occupy 80mm area, all macros in the design occupy 30mm area

• Utilization Factor be 70% means in the core area there should be 30% of free space for future use.
  std. cell area =80mm
  All macros area = 30mm
  Free space area =35 mm
  Total Core Area= 80+30+35 =145mm
  
  And this explained properly in below figure.

• Utilization Factor be 80% means in the core area there should be 20% of free space for future use
  std. cell area =80mm
  All macros area = 30mm
  Free space area =20 mm
  Total Core Area= 80+30+20 = 130mm

we can observe that area of the core decreases if we increase the utilization factor of the block or design

Full Adder

For three bit additions, full adder is used. First step in designing the full Adder circuit is to have truth table. Before that let see the binary addition rules.

Truth Table for Full Adder

Using the k-map, we can get the optimised Boolean expression for sum and carry.
Boolean expression for sum

Boolean Expression for carry

From the above booleaan expression , we can Implement of sum and carry as shown below

How to remove maximum fan out violation for a cell?

Fan-Out of the gate is defined as number of gate inputs it can drive. Every cell/gate will have limitations and we can get the maximum fan limits from LIB file which are provided by vendor or foundry. If Fan out violation occurs for a design or on pin, we can remove the violation by inserting a buffer. 

For example, consider a two input OR gate which has a max fan out limit of 3. Assume in a design this OR gate is connected to 5 loads thus violating the Fan out violation. Violation can be removed by inserting a buffer with fan-out more than 3 as shown below. After inserting the buffer, the OR gate will have a fan-out of 3 which is within the limits.

       

                                            Fig 1 : Fan out of OR gate with out buffer

                              Fig 2 : OR gate with buffer

Target Libraries, Link Libraries, Physical Libraries

Traget Library:

The target libraries are the technology library needed to map to design during synthesis. we have to specify the target library with the pointer variable traget_library.

set target_library {“…………..” “…….”}

Link Library:

The link libraries are the technology library used to describe the function of mapped cells prior to opitimization and these are specified with the variable pointer link_library.

set link_library {“____.db” “___.db”

Physical Library:

The physical libraries are the technology library includes the physical design rules and physical view of the standard cells and these are specified with the pointer variable physical_library.

set physical_library {“____.pdb” “____.pdb”}

Perl Series III

How to remove the repeated words in a line, like shown in file below

===============================

vlsispace = "bin/trail/world", "bin/drive/space", "usr/bin/vlsi", "bin/trail/world";

string1 = "bangalore", "chennai", "newyork", "bangalore";

fruit = "apple", "orange", "grape","apple"; 

==================================

In above file few words are repeated in each line and those extra words need to be removed from the lines

First using grep expression try to capture the line and then split the pattern using a split command. This step will convert the string to a array format .
@fields = split(/delimiter/, “pattern”);
Next step try to remove the repeated word in the array. Finally once all the words are unique, join the array to string with the delimiter that was used to split the string. Join command is used to join the words in array
$string=join(“delimiter”,@array)

There are many ways to write the logic and one of the way is given below

==========================================================

#!/usr/bin/perl

open(rh,"","new_file") or die "couldnt open the file, $!;

foreach $line() {

if($line =~/(\".*\");$){

@fields split(/, /,$1);

my %hashes;

my @unique;

foreach my $value(@fields){

if(!$hashes{$value}){

push @unique $value;

$hashes{$value}=1;

}}

$string = join(", ",@unique);

print wh "$string;\n";

}

else {

print wh $line;

}}

close(wh);

close(rh);

==========================================================

This perl scprit will remove the repeated word from the line and prints a new file with a unique word in a line.

Half adder

Adder is one of the important combinational circuit to perform the Arithmetic Logical operations.

Half Adder:
A half adder is used to add two single digit binary number. First step in designing the Half Adder circuit is to have truth table. Before that let see the binary addition rules.

Truth Table:

Using the k-map, we can get the optimised Boolean expression  for sum and carry.
Boolean expression for sum

Boolean expression for carry

From above equations , the Half adder circuit implemented as below

                                                      Half Adder

Why NAND gate is preffered over NOR gate

 NAND gates are preferred over NOR gates, because of below factors

• Delay offered by NAND gate is less than NOR gate
• Also NAND gate takes less size.
• Low to high and high to low time are more symmentrical in NAND based design than in NOR based design

Before understanding why NAND gate offers less delay compare to NOR gate, we need to understand the pmos and nmos in circuit level and also different delays.
RC equivalent circuit of nmos and pmos with width k is shown in fig 1.

                                                    Fig 1: NMOS and PMOS

Lets us analyse the rc model of inverter (with k_n=1 and k_p=2) which is connected to another inverter of same k_n and k_p value as shown in below fig 2.

Have you noticed width of pmos(k_p) is twice the nmos(k_n), what could be the reason?

In inverter nmos and pmos are connected in series and therefore current through the pmos must be equal to nmos. As mobility of holes are less and offers more resistance, thus to increase the flow of holes channel width of pmos is made twice that of nmos channel width. The elmore delay of the previous ciruit is show below and from this circuit we can calculate all the delays of circuit.

                     Fig 3: RC model of two inverters connected back to back

Delay of any device can expressed as sum of parasitic delay and effort delay/stage effort that depends on complexity and fan-out of the gate
d=p+f 
p————–is the delay of the gate/device when no load is attached.
f—————is the effort delay
f=gh
The complexity is represented by the logical effort, g and this defined as ratio of input capacitance of a gate to the input capacitance of an inverter that as same drive strength (i.e. delivers same current).

Electrical effort is denoted by h, If the load does not contain identical copies of the gate, the electrical effort can be computed as
h = C_load / C_driver
C_load is the capacitance of the external load
C_driver is the driving capacitence of the gate

Now let us consider a two inputs NAND gate and NOR gate , both drives a same external load(C_out =4). Parasitic delay for inverter, NOR, NAND gates approximately equal to number of inputs. Therefore parasitic delay for 2 i/ps NAND and NOR gates are approximately equal to 2 and this delay increases as the no of inputs increase. Assume both NAND and NOR gate have same driving capacity( C_driver =4) and drives same load capacity ( C_load =12) , then electricl effort(h) for both gates will be equal to 3.

The logical effort the gates are follows

                                      Fig 4 : NAND Gate

                                 

                             

                                             Fig 5: Nor Gate

                                              

Delay offer by NOR gate is 7ns which is more than the delay offered by NAND gate.Thus the circuits design with NAND gate offers less delay compared with the ciruit design with NOR gate and therefore as a engineer we need to prefer NAND gate over NOR gate in circuit designing.

Test coverage, Fault coverage

Test coverage and Fault coverage are the two important quantities which measures how good the DFT logic was implemented on core design for controllability and observability of a design.

Test Coverage:
Test coverage is a measure of test quality of DFT, is the percentage of faults detected from among all testable faults. This is the number of most concern when you consider the testability of the design

Fault Coverage:
Fault Coverage consists of the percentage of faults detected from among all the faults that the test patterns generated by the tool

Where DT is detected faults class includes all the faults that the ATPG identifies as detected and this are classified into two groups

• Det_simulation (DS)
• Det_implication (DI)

PD – posdet or possible detected fault class includes all the faults that fault simulation identifies as possible detected but not hard to detect
Let us see how the test coverage and fault coverage was calculated from snap shot of status report

                                                  report_statistics of faults

From the report Total no of faults are given as 302778
Faults due to unused pins (UU), Tied pins (TI), Blocked Pins (BL), and redundant logic (RE) are untestable by tool and this faults must be excluded from the total number of faults while calculating the Test Coverage and considered while calculating the Fault Coverage.

UU+TI+BL+RE => 4984+1076+12+1072 = 7144

Thus Testable faults are given asTotal Faults – (UU+TI+BL+RE)
Total faults detected during simulation (DS) and implication (DI) are

DS +DI => 202752+75601+16 = 278369

In general posdet_credit will be set to zero and with this above faults numbers we can have Test Coverage and Fault Coverage

  

In this process TC and FC are calculated and we need to achieve 99 % Test Coverage for Stuck At fault model and 95% Test Coverage for At Speed fault model

Universal Gates

In one of my interview, the interviewer asked why AND, OR gates are not called as universal gates. I couldn’t answer to his question. Let us know why NAND and NOR gates alone called has Universal gates.

Universal Gates
A logic gate which can implement any Boolean function without need of other logic gates is called Universal Gate. From the above explanation we can conclude NAND and NOR gates as universal gates, which means we can implement any logic gates using these two gates.

Implementation of logic gates using NAND gate
1.       Inverter

             

2.       AND GATE 

3.       OR GATE

Implementation of logic gated using NOR gate

1.       Inverter 

             

2.       AND GATE

             

3.       OR GATE

           

AND, OR ,NOT which are basic gates can be implemented by using NAND or NOR gates as shown above, similarly any logic can be implemented using NAND or NOR gates. And so these gates are called universal gates.

When you are asked to  design a gate using one of the universal gate, which gate is better to use? 
NAND gate is more commonly used compared to NOR gate because they offer less delay compared to NOR gate and also occupy less area.

Multi Voltage Domain

Why we need the multi voltage domains in SOC, Can’t we design a chip with single voltage?
Yes we can design a chip with a single voltage when we are working on less frequency where speed is not main priority.

                                          Source : Internet

If someone is least interested in speed of operation like snail which will ultimately reach the destination but the time taken to reach the destination can be 1 hour or 5 hours, then we can design a SOC with single low voltage domain which operates at low frequency. And power consumption will be less as power is directly proportional to V²

If a person want the results in nano seconds, then the device must work at high frequency. With applying high voltage, high frequency can be achieved with a drawback of power loss, as power is directly proportional to V²

 Ex: Assume computer need to add 2 and 2, output will be 4. The time taken to execute the instruction and display the output depends on frequency of CPU, it will take more time if CPU is working on less frequency (low voltage). If the computer need to execute given instruction in nano seconds, the CPU should operate on high frequency (high voltage) with huge amount of power loss

Because of this huge power loss, it is not practical to design a SOC with single voltage domain at high frequency. To reduce the power consumption design was divided into multiple voltage or power domains each with its own supply voltage and this type of approach is called multi voltage design. The multi voltage design is based on realisation that in SOC design, different blocks will have different objectives for instance processor need to run at high speed and the processor block should be supplied with high supply voltage. On other hand USB block may run at fixed, relatively low frequency. In this case low supply voltage required for operation. Few blocks will be powered off when they are not in use.
Also multi voltages are required in RAM

• Low voltage to maintain memory contents when the memory is not being accessed
• Higher Voltage that supports read and write action

There are different Multi voltage domain strategies:

• Static Voltage Scaling (SVS)
• Multi-Level Voltage Scaling (MVS)
• Dynamic Voltage and Frequency Scaling (DVFS)
• Adaptive Voltage Scaling

To conclude, to reduce the power consumption at higher frequency, multi voltage domain is one of the technique used.

N-type and P-type semiconductor

In semiconductor physics Group IV( in IUPAC Notation it is Group 14) contains Carbon (C), Silicon (Si), Germanium (Ge), Tin (sn), Lead (pb), Flerovium (Fl), all this elements contains 4 electrons in its outer shell nothing but four valence electrons. Out of all this elements Silicon (Si) is widely used in fabrications of chips because of following advantages.

• Silicon reacts with oxygen and forms oxides itin a controlled manner and forming a layer of stable oxide which reduces thesurface recombination velocity
• Its hardness that allows large wafer to behandled safely
• Its thermal stability, up to 1100^o C,that allows high temperature processing related to diffusion, oxidation andannealing
• Primarily available for low cost

By adding an impurity conductivity of material can be increased and depending on the impurity added we can have two types of semi-conductors
N-type Semiconductor :
When the group V element is added to the intrinsic or pure semiconductor (silicon or Germanium), the resulted product is said to be an n-type semiconductors. The group V elements are phosphorus, arsenic, antimony and this elements have five valence electrons. When Phosphorus is added to silicon, it forms four covalent bonds with neighbouring silicon atoms. The fifth valence electron of phosphorus atom does not involve in formation of covalent bond and this electron is free to move in structure. As the group V elements donates a free electron, these elements are called donors. With small addition of impurity (phosphorous) provides millions of electrons which are majority carrier in n-type semiconductor

                                             N-Type Semiconductor

P-type Semiconductor
When the trivalent impurity or acceptor impurity added to Silicon (Group IV), the resulted product is said to be p-type semiconductors. The group III elements are Boron (B), Gallium (G), Indium (In), Aluminium (Al) and these elements has three valence electrons. When Boron in added to Silicon as impurity, three covalent bonds are formed with three neighbouring silicon atoms and in fourth covalent bond, only silicon atom contributes one valence electron, while the boron atom  is in short of one valence electron. Thus the fourth covalent bond is incomplete with shortage of electron and this missing electron is called hole. With small addition of impurity (boron) provides millions of holes which are majority carriers in p-type semiconductor

                                                       P-Type Semiconductor

VIM editor series II

Here is second post on the vi editor commands.
Insert a file content

:r file_name or file_path

example: Need to paste the info from file B to A      

           Copied the content to file A from file B using command :r B 

Repeat the Last Action 

. (dot or aka period or full stop)

• Suppose you press dd to delete the line. Next if  you want to delete the next line you press dd or .(dot)
• Suppose you press Hi and you like to repeat the action then just press .(dot) in normal mode of vi editor

Display the line numbers
enable the line number 

:set number or :set nu 

disable the line numbers

:set nonumber or :set nonu

Reversing the Order of lines 

:g/^/m0

:—- start the command line mode

g—- action will be taken all lines in the files
^—-matches the starting of the line
m—moves the elements
0—Is the destination line, beginning of the buffer

If i need to reverse the lines between a certain range(like between 30 and 40 lines), then we can use the following command
:30,40g/^/m29

To control the position of split window
:set splitbelow or splitright

Undo and Redo
In normal mode conditions

• use u for undo the action
• cntrl+r for redo the action 

Conductors,Insulators, Semiconductors

At present we can find chips in every application, even in space application. And silicon (Si) is widely used material for manufacturing the chips. Semiconductors materials are used mostly in chips. Based on Energy Band gaps the metals are classified into

• Conductors
• Insulators
• Semiconductors

A band gap is the distance between the valence band of electrons and the conduction band of electrons. A band gap is minimum energy required to excite an electron to conduction band from a valence band

Conduction band is the band of orbitals that are high in energy and are generally empty at room temperature. In reference to conductivity, it is the band which accepts the electrons

Valence Band is the band occupied with molecular orbitals which are lower in energy. When there is temperature raise, the electron will jump from the valence band to conduction band, making the materials conductive

Fermi Level is defined as highest occupied molecular orbital in valence band at 0 k. The Fermi level lies between the valence band and conduction band because electrons will eventually occupy the low energy states at room temperature. Fermi level can be considered as sea of electrons above which no electrons will exits. Fermi level changes as the solids are warmed and electrons are removed or added to orbitals

Conductors
In conductors the valence band and conduction bands are overlapped. This overlap causes the valence electrons to move freely in conduction band which results in conduction. Metals, living beings are few good conductor materials. This materials offers less resistance to flow of electrons.

                                            Fig 1 : Conductors

There is no band gap in conductors and electrons are free to move to conduction band.

Insulators
In Insulators the conduction band and valence band are separated with large band gap. This prevents the electrons movement between the valence band and conduction band. And there will be no conductivity. Wood, plastic, glass are few of the insulating materials. This material offer more resistance to flow of electrons.

                                         Fig 2: Insulators

Semiconductor
In the semiconductors the band gap energy is small, as a result with small amount of heat or energy electrons get excited and jumps from the valence band to conduction band. There will be conduction of electricity and with small amount of doping conductivity of materials will be increased. In this material we can control the flow of electrons.

                                        Fig 3: Semiconductors

There are two types of semiconductors.

• N-type Semiconductor electrons are majoritycarrier for electricity and hole are minority carriers
• P-type Semiconductor holes are majoritycarrier for electricity and electrons are minority carriers