how to design the better transistor which has high on current and low off current

Speed of the transistor is decided with Ion and Ioff. On current was increased as we go down the technology node because less Vt is required for small channel length and delay of the device is also  reduced.When Device is off(i.e Vgs =0 and Vds=Vdd) there will be subthreshold current which contributes to the Ioff current and this current must be maintained low to reduce the static power. For better operation of the devices on current must be high and off current must be low.

• Ion current was increased with decrease in Vt ( this is reduced for every latest technology node)
• Ioff must be maintained low and this is achieved by reducing the subthreshold swing. Vt can be increased to reduce the Ioff but this will affect the Ion current of the device and delays of the devices will be affected.

Below image gives the equations of Ioff current and sub threshold swing 
W  represents the width of the channel
 L    represents the length of the channel
Vgs  represents the gate to source voltage
Cox  represents the oxide capacitance
 Vt represents the threshold voltage of the devices.

 From the above equations we can say Ioff can be reduced by changing S(subthershold swing) ,this can be achieved two ways

• By Increasing the Cox i.e. using thinner oxide 
• By reducing Cdep of the device, this can be done by increasing Wdep.

                                              nmos(source:internet)

Oxide capacitance can be increased by using the thinner oxide or high dielectric materials. Thickness of the oxide layers cannot be reduced beyond the 1nm , if it is beyond the 1nm , there will be a breakdown of the oxide material and tunnelling leakage current increases.
Because of the above limitation in thickness researchers started using the high K dielectric materials. Like 6nm thick HFO2 is equivalent to 1nm thick of Sio2 in the sense that both the films produce the same Cox. Like very solution as some negative effect, high K dielectrics are highly unstable and they react with the substrate.By inserting a thin Sio2 layer  between substrate and dielectric material the chemical reaction can be reduced. High K dielectric materials offer lower surface mobility than Si/Sio2 which is a disadvantage . 
Cdep can be reduced by increasing the Wdep, this can be done by decreasing the doping concentration because Wdep is inversely proportional to Nsub (doping concentration).
For a Device to work properly, we need to change Wdep, Tox, Xj(drain junction depth) proportional  to change in channel length 

   

     

     

   

Setup time and Hold Time

Any digital design should be free from setup and hold violation. First, we will understand what is Setup and Hold time. Below fig is simple circuit with launch and capture flipflop, these are ideal flip flop (means setup time and hold time are zero)

Setup time is the minimum amount of time a synchronous data input should be held steady before the clock event so that the data input is reliably sampled by the clock event.
Hold time is the minimum amount of time a synchronous data input should be held steady after the clock event so that the data input is reliably sampled by the clock event.

Any design to work perfectly setup and hold slack must be positive. What is slack?
Slack is defined as difference between required arrival time to actual arrival time of the signal. There are setup and hold slack. Design works well if both the slacks are positive and there will be violation if any of them or both are -ve
Setup Slack is the difference between the Required time and Arrival time of the signal at capture flip flop. During the setup calculation we must take max delay values in data path and min values in clock path and the setup slack must be greater than zero for violation free circuit. Setup check is carried at next clock edge.

Setup slack=RT-AT
RT——-required time
AT——-arrival time
RT= clock_period(tp)+clock_network_delay(tc)-setup_time(tsu)
AT=flip_flop_delay(tc2q) +wire_delay(tw)+comb_delay(td)

Hold Slack is the difference between the Arrival time and the required time of the data signal. During the Hold calculation we must take min delay values in data path and max values in clock path and the hold slack must be greater than zero for violation free circuit. Hold check is done on same clock edge

Hold Slack =AT-RT
RT= clock_period(tp)+clock_network_delay(tc)+hold_time(th)
AT=flip_flop_delay(tc2q) +wire_delay(tw)+comb_delay(td)

Note: As hold analysis is carried on same clock, we must make clock_period to zero(tp=0)

How to we overcome the setup or hold violation
Setup violation occurs when the data arrives late at the capture flip flop and this can be avoided by reducing the delay in the data path. Delay in data path can be reduced in different steps

• LVT cells offers less delay, we can swap the HVT cells to LVT cells
• High drive strength cells delay is less compared to low drive strength and we can swap between the low drive strength cell to high drive strength cell, but we need compromise with the power.
• If we can comprise with speed of the design, then clock frequency can be reduced to avoid the setup violation.

Hold violation occurs when the data arrives early at the capture flip flop and we need add delays in the data path to avoid the hold violation. We can do any of the steps to increase the delay in the data path    

• We need to add the buffers in the data path
• Swap HVT cells to LVT cells
•  Swap high drive strength cells to low drive strength cells

Design For Testability

DFT means Design for testability, where logic will be implemented or inserted in the core design at RTL stage(Now a days most of the company prefer at RTL stage) or Netlist stage. This test circuit verifies that core design does not have manufacturing defects focusing on circuit structure rather than functional behavior.

Manufacturing defects may include

• Short circuits
• Open interconnects
• Power and ground shorts

Manufacturing defects remain undetected by functional testing and these can cause undesirable behaviour during circuit operation. DFT helps to find the manufactured defects and improves the quality, yield of products.

Now you may wonder what is the use of Functional testing.Functional testing verifies your circuit performs .For example assume that your design is an Half adder circuit , Functional test verifies that circuit performs the addition operation and computes the correct results over the range of patterns

Temperature effects on Mobility

In a Cmos or Finfet the current flow is due to movement of the electrons and holes. The free movement depends on the mobility of electrons/holes and factors affects the mobility are lattice scattering and impurity scattering which are dependent on the temperature.

Lattice scattering
Atoms vibrate more as the temperature increase and this results in collisions with another atoms and causing carriers (electrons/holes) to be free. This collective vibration is called phonon, thus it is also called as phonon scattering. Therefore with increase in temperature the vibrations of atoms increases and more carries are scattered from atoms, this increases the collision between the electrons and reduces the mobility. Despite the decrease in mobility, conductivity increase with the temperature as carrier concentration increases with temperature. Mathematical relation between the mobility and temperature as follows

 Impurity scattering
Impurity scattering is observed in the doped semiconductors. At room temperature the impurities are ionized, and there is electrostatic attraction between the electrons travelling in the lattice and the impurities. As temperature increases the mobility of electron increased which is quite opposite to the Lattice scattering. Impurity scattering is more dominate only at low temperature in doped semiconductors. For better understanding, the electron can travel faster with increase in the temperature and it can escape the attraction forces of the impurity ions. Mathematical relation between the mobility and temperature as follows

we can observe only lattice scattering in intrinsic semiconductor where as in doped conductors we can see lattice and impurity scattering which effects the mobility of the electrons/holes.

In less doped semiconductors, the lattice scattering dominates and thus mobility decrease with increase in temperature.

For heavily doped semiconductors at low temperature as temperature increases the mobility of electrons increases since impurity scattering dominates and at high temperature the mobility decrease since lattice scattering dominates

                                           source: Image from google

Drive Strength of devices

What is drive strength of device?
Drive strength is the current capability of the device, which is capable to drive the fan outs/output loads. The drive strength of the devices which is nothing but current carrying capacity can be increased by reducing the ON Resistance and Vice Versa. Thus ON resistance can be varied by varying two parameters of the devices

• Width(W)
• Channel Length(L)

Case: I 
ON Resistance is reduced with increasing the width of the channel as shown in the figure. W1 < W2, and L is same.

Width of the channel adds up to the height of the standard cell and if there is any restriction on the height of standard cell, we need to avoid changing width parameter of the cell/device(nmos or pmos).Instead we can the increase the width of the device indirectly by constructing more than one gates (fringes) and connecting them in parallel as show in below figure which increases effective width of the device.

The drive strength 1x, 2x, 3x … means width of the device is 1W, 2*W, 3*W respectively.

Case II
By changing the channel also we can change the driving strength!!!……. But for technology node channel length is constant, then how can channel length be changed?
For a given technology node there will be  more than one channel and this details are provided by fab people. I mentioned on channel length in my previous post Technology/Process Node
There raises a question when we need to upsize the drive strength?
When the load capacitance is more than the internal capacitance as a result charging time increases and delay increases, to reduce the charging time/delay we have to upsize the cell.

Clarification:
Lets us consider a CMOS design which has both nmos and pmos.The height of the cmos(standard cell) is equal to the sum of Vdd’s widht, pmos channel width, diffusion spacing between pull-up and pull-down transistors, nmos channel width and width of Vss metal layer. A clear picture was shown below. Thus changing the width of the channel in pmos or nmos effects the height of the standard cell

                                          CMOS LAYOUT

Where L represents the channel length of cell (pmos or nmos)
           W represents the channel width of cell(pmos or nmos)

False Paths:set_false_path

During the timing analysis, tools verifies whether logic paths meets all the constraints defined in the SDC (Synopsys design constraints) and reports violation if any logic paths doesn’t meet the required timings. And the tools are not intelligent enough to find which logic path was true or false path. Therefore, we must inform the tool which are the false paths before performing the timing analysis. Few cases are mentioned below.
Case I

During the Functional mode the select line of mux is tied to 0 and tool should not perform the timing analysis on this path (marked in orange) which will be active during DFT test mode. This information must be provided to the following command
set_flase_path -to <list of end points>

Case II:
We need to add false path on the pins which are tied to low or high (static signals). As they are static signals, timing checks are not necessary.
set_false_path -from [get_ports A]

Case III:
If two clocks are not related to each other (Asynchronous) then we must define these paths as false path. In this case to avoid any setup/hold violations at capturing registers some synchronizers technique must be employed. Few of the techniques are

• Two flop Synchronizers
•  FIFO
•  Handshaking protocol

set_false_path -from CLKA   -to CLKB

In case of the two flip flop synchronizers as show in above figure timing checks are not necessary between the Launching flop and the 1^st stage of the synchronizers. Therefore, we have to consider the signal to Flop FF2 as false path

Clock Gating

Clocking gating is technique in which the clock signal is given to Flip Flop through AND/OR gate with enable signal as shown in fig 1. With this design there will be a glitch when the control signal is enabled after the clock rise edge. By using Integrated clock gating we can avoid the glitches.

                                                Fig 1: Simple clock gate

ICG is modification of a clock gating technique, and the enable/controls signal was synchronized with clock before gating the enable/control signal and clock signal to avoid the glitches and to reduce the dynamic power consumption. ICG with AND gate and negative flip flop is shown in fig 2. We can also use, OR gate and positive edge triggered flip flop to build a ICG. 

                                 Fig 2 : Integrated Clock Gating

Glitch free output is achieved from ICG circuit as shown in fig 3. And if we are not using the FF enable /control signal will not be synchronized with clock, which results a glitch in output. 

                                                  Fig 3 : Wave Form

Technology/Process node

If you look back in time every semiconductor companies started to scale their device by reducing the area to half of its previous version.Reduction in size of devices reduces the effective capacitance, which in  turn reduces the delay (by 30 %) and makes the devices run faster. As a result Operating frequency increases.Finally to keep the electric field, the voltage for the new node need to be reduced by 30 % and this way for each technology node upgrade transistor density doubles with same power consumption

To double the density of the devices ,the contacted Poly pitch(CPP) and minimum metal pitch (MMP) need to be scaled down by roughly 0.7x each node. In other words, scaling of (7*CPP)*(.7MMP)=area/2. In this way future technology node was decided
180nm*.7 ≈ 130nm
130nm*.7 ≈  90nm
90nm  *.7 ≈  65nm
65nm  *.7 ≈  45nm
45nm  *.7 ≈  32nm
32nm  *.7 ≈  22nm
22nm  *.7 ≈  15nm
15nm  *.7 ≈  10nm
10nm  *.7 ≈   7nm
7nm*.7 ≈ 4.9nm

Before 32nm, the process node roughly corresponds to the minimum value of drawn gate length and the channel length used to be lower than the node value considering overlap from source and drain regions on gate area. Digital circuits that are synthesized using standard cells and the height ,width of standard cells are multiple of CPP and MMP as shown below

For 32nm process, different foundries had the value of these pitch around 110-130nm. if a foundry can fit a complete MOSFET device i.e source , channel and drain in one gate pitch, the absolute value of gate length would not matter and the area of the digital IC will scale with the product of metal pitch and metal pitch. So to reduce the area further, it makes sense to reduce the pitches. By scaling metal and gate pitchs, foundries continue to offer process improvements without reducing effective channel length. And with this approach ,the correlation of gate length and the node name became dilute.In the 2009 ITRS, the references to the term ‘technology node’ were eliminated. Also, roughly after this time, the process nodes scaled in a way that could be described as equivalent scaling in which the 3 dimensional device structure was improves or scaled to improve performance. As far as the names of latest process nodes such as 14/10/7 are concerned they are simply a commercial name for a generation process technology, with no relation to gate length, metal pitch or gate pitch.

Now if i say 28nm technology , we have 28nm, 30nm, 35nm, 40nm different gate length options. And the technology node will take the minimum gate length.Every thing  looks good till here but why we need different gate length for a technology node because in some design the minimum timing is met with 30nm gate length and in some other design minimum power is achieved with different gate length.  For 32nm process, different foundries had the value of these pitch around 110-130nm. if a foundry can fit a complete MOSFET device i.e source , channel and drain in one gate pitch, the absolute value of gate length would not matter and the area of the digital IC will scale with the product of metal pitch and metal pitch. So to reduce the area further, it makes sense to reduce the pitches. By scaling metal and gate pitchs, foundries continue to offer process improvements without reducing effective channel length. And with this approach ,the correlation of gate length and the node name became dilute.In the 2009 ITRS, the references to the term ‘technology node’ were eliminated. Also, roughly after this time, the process nodes scaled in a way that could be described as equivalent scaling in which the 3 dimensional device structure was improves or scaled to improve performance. As far as the names of latest process nodes such as 14/10/7 are concerned they are simply a commercial name for a generation process technology, with no relation to gate length, metal pitch or gate pitch.

Why mosfet are replaced by FD-SOI ,Finfet below 28nm technology?

During my internship days at ST Microelectronics, Greater Noida,  I saw a poster which describes about the FDSOI technology. In those days I used to think what is the difference between finfet and FDSOI. In these post we will discuss about why FDSOI or Finfet was required.

Even though we had mosfet, industry is driving towards new technologies like Finfet, Fdsoi. For various reasons industries are forced to design a soc/chip which occupies less area, consumes less power, and also gives better performance, even though all three parameters cannot be achieved at same time. By shrinking the devices(reducing the channel length) we can reduce the area occupied, reduce the power, and increase the performance.
But as we go below 28nm in bulk planar transistors, leakage current increases as a result power consumption increases. Some of the Limitation for  planar transistor that prevent the usage of them below 28nm are.

• Gate control on the channel is not 100% and this results in higher leakage current. Following are the sources for leakage power
  • Reverse bias p-n junction leakage
  • currentSub threshold leakage current           
  • Tunnel current through the oxide           
  • Gate current due to hot carrier injection           
  • Gate induced drain leakage current           
  • Channel punch through current
• Device is not truley OFF

To overcome this limitation designer need to make the channel thinner so that gate control over the channel increases.This was the main reason why Finfet and Fdsoi technologies are invented

Finfet
Instead of having a planar transistor with the channel  in the silicon wafer, the channel is created as a thin vertical fin and the gate is wrapped around three sides of the fin. Now gate as more controlled over the channel and leakage power was reduced. Switching speed is more compared to mosfet devices

  Fig 1: FinFet

For PMOS
– Mo (4.95 eV)
For NMOS
– Ta (4.25eV)/ Mo stack
-Ta Inter Diffusion in Mo

FD-SOI
These approach was developed by ST Microelectronics. In FD-SOI instead of making the channel area out of the silicon wafer itself, start with an insulator and add a thin layer on top it to form the channel.Then build the planar gate on top of it in normal, along with source and drain. With insulating layer at the back, the channel is thin and like in Finfet case, it is well controlled by the gate. Unlike in planar transistor or mosfet, in FD-SOI can have multiple Vt(threshold voltage) by changing the body bias of the FD-SOI and this is one of the advantages where we can control the Vt of the devices even after  manufacturing it.

Fig 2 : FDSOI

In mosfet the channels are doped but in case of FD-SOI and Finfet the channels are not doped, these eliminates the random dopant fluctuation, which is one of the biggest sources of threshold voltage variability. This undoped channels gives the ability of changing the Vt of the devices(FD-SOI) by changing the back body bias voltage.

Difference between LEF and DEF files

LEF –Library Exchange format
All the physical information of the design can be provided in the LEF file, these files are loaded into the pnr tools instead of loading the full design which takes huge memory and huge time to load and there are two types of LEF files

• Technology LEF file
• Cell LEF file

A technology LEF contains all the placement and routing design rules, process information of the technology. For best practice try to load the technology file first and then load the other lef file. A cell LEF files contains all the physical information of the macros and the standard cell

DEF -Design Exchange format
A DEF file is used to describe all the physical aspects of a design,

• Die size
• Connectivity 
• Physical location of cells and macros on the chip. 

It contains floor-planning information such as –

• Standard cell rows
• groups- Placement and routing

Blockages

• Placement constraints
• Power domain boundaries. 

DEf file also contains the physical information of pins, signal routing ,power routing etc

In scan chain why negative edge flops are followed by positive edge flip flops

While scan stitching of the scan cells in any design, the tool will make sure that all the negative triggered flip-flops are placed first in the scan chain and then positive triggered flip flops. A scan chain contains 

• All positive edge flip flops
• All negative edge flip flops
• A mix of positive and negative edge flip flops

There is no issue if a scan chain contains only negative or positive flops, problems arrives when there are both -ve and +ve flops. In general, the tool places all the negative flip flops first then followed by the positive flops. Here we might struck with a question, why not the positive flops first then followed by negative flops? Well there is reason to it.

For better understanding assume a scan chain with two positive edge flip flops and two negative edge flip flops as shown in the below figure 1 and we need four clock cycles to transfer the data through the given four flip flops, But if we place the positive flip flops first followed by negative flip flops then the data will be transfer out with in three clock cycles which is not good for a design and we might get the hold violations.

            

If the design needs the positive triggered flops to be placed first in a scan chains, then to avoid the two shifts in single clock cycle,place a negative latch (lockup latch) at the intersection junction of the positive and negative flops. Hold time violation can be meet during DFT shift mode using lockup latch.

                                        Fig 2: Positive FF_Latch_Negtive_FF

Or we can place all the negative flip flops first and followed by positive flops and thus we can avoid the data shift twice in a clock cycle.

                                  Fig 3 : Negative_FF_Positive_FF

Unix Basic Commands III

In Vlsi Industries an engineer must be strong in the Digital Design, Analog Design and he/she should be strong in scripting language, shell commands. Few basic shell commnads which are widely used

• cat <file_name>——-display the information in a file without opening the file
• grep ————to search a word in that file
  syntax: grep [options] pattern [files]
  options Decsriptions
  –c: This prints only a count of the lines that match a pattern
  -h: Display the matched lines, but do not display the filenames
  -i: Display the matched lines, but do not display the filenames
  -l: Displays list of a filenames only
  -n: Display the matched lines and their line numbers
  -v: This prints out all the lines that do not matches the pattern
  -e exp: Specifies expression with this option. Can use multiple times
  -f file: Takes patterns from file, one per line
  -E: Treats pattern as an extended regular expression
  -w: Match whole word
  -o: Print only the matched parts of a matching line, with each such part on a separate output line
• mv –——– this is commad which is used to rename or move the file/directory
• cp –rf <soucre> <destination>————copy the file or directory to some other place
• cat filename > filename1 copies the information from filename to filename1
• pwd — gives full path of the present location
• wc –word count
• head –<no of lines to disply from top> <file_name> ——-gives the information of lines from top of the file
• tail -<no of lines to diplay from bottom> <file_name>——-gives the informations of lines from bottom of the file
• pipeline |  —–out put from the command on left of pipeline will be the input for the command on right of pipeline
  ex: ls | tee file.txt
  ls list the file/directory in the folder and then this will be the input to next command and the tee will  store the information in file.txt

Unix Basic Commands II

In Vlsi Industries an engineer must be strong in the Digital Design, Analog Design and he/she should be strong in scripting language, shell commands. Few basic shell commnads which are widely used

• To change the permission of a file or directory
  • chmod ——used for changing the  write/read/execute permissions

u,g,o individually represent the permission for user/owner ,group and others in same order 4 stands for read 2 stands for write 1 stands for execute 0 stands for no permissions

• chown——To change the owner and group of file  or directory
  • chown owner <file_name> –if only owner is given , that is user made owner of the given file and  file group is not changed
  • chown owner.group or owner:group <file_name> —  with this the user is made owner of the file   and the group of a file is changed

Unix Basic Commands I

In Vlsi Industries an engineer must be strong in the Digital Design, Analog Design and he/she should be strong in scripting language, shell commands. Few basic shell commnads which are widely used

• To get the information of commands
  • man <command_name>
    ex: man cd
  • <command_name> –ls
    ex: cd —ls
• To Change the Directory
  • cd <directory name/directory path>
    ex: cd directory name<or>directory path
    cd… ——– comes out of present directroy
• To list out the files or directory in present location
  •  ls gives the list of files or sub directories in present directory
  • ls -a gives the list of hidden files
• To link the file
  • ln <file_to_be_linked> instead of copying the file to we can link the file and thus save the space
• To create a directory
  • mkdir <directory_name>
    ex: mkdir vlsispace
  • mkdir –p  <directory>/<sub_directory>  creates a directory and then creates a sub_directory
    ex: mkdir -p /vlsi/space
• To create the files
  • touch  <file_name>  —— creates a empty file
  • vi<or>gvim<or>nedit <file_name> ——- this editors are used to create a file and the edit, save the files.
• To remove the files or Directories
  • rmdir  <directory_name>—— removes the directory
  • rm <file_name> —— removes the file
  • rm –rf  <file_name>or <directory_name>—– remove the directory or file

Can hold violation be removed after chip was fabricated

Can we remove the hold violation once the chip was out from fabrication unit?
After the chip was manufactured, if there are any setup violations in the design, can removed by reducing the clock frequency of the design at the cost of device performance.Now if the hold violation was found after chip was out,we have to discard the the chip. Theoretically there are few methods to remove the hold violations, but in practical cases these may not be implemented on the chip

1. By reducing the supply voltage and frequency, we can increase the delay of the cell and thus meet the hold violations
2. By increasing the temperature, propagation delay of the cell decreases and thus we can met the hold violation. However for 65nm and below technology, temperature inversion phenomena was observed and thus delay decreases as temperature increased. For lower technology nodes increasing the temperature worsens the hold timing.

SDC (Synopsys design Constraints)

SDC abbrevates to Synopsys design constraints which has information of timing, area and power constraints for the design and this files are in TCL format. The front end( rtl designer) adds the required constraints to the design and then dft team adds the required constraints to sdc file. In few companies STA engineer will responsible for creating the SDC file. Below are the list of commands with which SDC files are created.

• Operating conditions
  • set_operating_condition
    Sets the required operating conditions for the timing analysis. Type of analysis can be single, wc_bc or on chip variation. We can find the operating condition in the libraries that are defined using operating_conditions command Operating conditions
• System Interface
  • set_drive
    It specifies the drive strength of the input port and external drive resistance of the port
  • set_driving_cell
    Is used to model the drive resistance of the cell driving the input port
  • set_fanout_load
    specifies the fanout load on the output port of the cells
  • set_input_transition
    sets the transition time on the input port with respect to the clock defined
    ex: set_input_transition 0.4 [get_ports pin_name]
  • set_load
    set the value of capacitive load on the output port or net
• Design rule constraints
  • set_max_capacitance
    specifies the max capacitance on all the ports in the design
  • set_max_fanout
    specifies the max fanout for all the ports or on a design
  • set_max_transition
    specifies the max transition value for the port or on a design
  • set_min_capacitance
    specifies the min capacitance value for the port or on the design
  • set_resistance
    Specifies the resistance value for the given nets
    
    

Welcome to VLSI SPACE

This blog is started to write and discuss about Basics of VLSI domains and useful topics for VLSI engineers. We also update the latest/trending news of technology.