Speed of the transistor is decided with Ion and Ioff. On current was increased as we go down the technology node because less Vt is required for small
Month: September 2019
Setup time and Hold Time
Any digital design should be free from setup and hold violation. First, we will understand what is Setup and Hold time. Below fig is simple
Design For Testability
DFT means Design for testability, where logic will be implemented or inserted in the core design at RTL stage(Now a days most of the company
Temperature effects on Mobility
In a Cmos or Finfet the current flow is due to movement of the electrons and holes. The free movement depends on the mobility of
Drive Strength of devices
What is drive strength of device? Drive strength is the current capability of the device, which is capable to drive the fan outs/output loads. The
False Paths:set_false_path
During the timing analysis, tools verifies whether logic paths meets all the constraints defined in the SDC (Synopsys design constraints) and reports violation if any logic paths
Clock Gating
Clocking gating is technique in which the clock signal is given to Flip Flop through AND/OR gate with enable signal as shown in fig 1.
Technology/Process node
If you look back in time every semiconductor companies started to scale their device by reducing the area to half of its previous version.Reduction in
Why mosfet are replaced by FD-SOI ,Finfet below 28nm technology?
During my internship days at ST Microelectronics, Greater Noida, I saw a poster which describes about the FDSOI technology. In those days I used to
Difference between LEF and DEF files
LEF –Library Exchange format All the physical information of the design can be provided in the LEF file, these files are loaded into the pnr