Can we remove the hold violation once the chip was out from fabrication unit?
After the chip was manufactured, if there are any setup violations in the design, can removed by reducing the clock frequency of the design at the cost of device performance.Now if the hold violation was found after chip was out,we have to discard the the chip. Theoretically there are few methods to remove the hold violations, but in practical cases these may not be implemented on the chip
- By reducing the supply voltage and frequency, we can increase the delay of the cell and thus meet the hold violations
- By increasing the temperature, propagation delay of the cell decreases and thus we can met the hold violation. However for 65nm and below technology, temperature inversion phenomena was observed and thus delay decreases as temperature increased. For lower technology nodes increasing the temperature worsens the hold timing.