Clock Gating

Clocking gating is technique in which the clock signal is given to Flip Flop through AND/OR gate with enable signal as shown in fig 1. With this design there will be a glitch when the control signal is enabled after the clock rise edge. By using Integrated clock gating we can avoid the glitches.

Fig 1: Simple clock gate

ICG is modification of a clock gating technique, and the enable/controls signal was synchronized with clock before gating the enable/control signal and clock signal to avoid the glitches and to reduce the dynamic power consumption. ICG with AND gate and negative flip flop is shown in fig 2. We can also use, OR gate and positive edge triggered flip flop to build a ICG. 

Fig 2 : Integrated Clock Gating

Glitch free output is achieved from ICG circuit as shown in fig 3. And if we are not using the FF enable /control signal will not be synchronized with clock, which results a glitch in output. 

Fig 3 : Wave Form

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