# Technology/Process node

If you look back in time every semiconductor companies started to scale their device by reducing the area to half of its previous version.Reduction in size of devices reduces the effective capacitance, which in  turn reduces the delay (by 30 %) and makes the devices run faster. As a result Operating frequency increases.Finally to keep the electric field, the voltage for the new node need to be reduced by 30 % and this way for each technology node upgrade transistor density doubles with same power consumption

To double the density of the devices ,the contacted Poly pitch(CPP) and minimum metal pitch (MMP) need to be scaled down by roughly 0.7x each node. In other words, scaling of (7*CPP)*(.7MMP)=area/2. In this way future technology node was decided
180nm*.7 ≈ 130nm
130nm*.7 ≈  90nm
90nm  *.7 ≈  65nm
65nm  *.7 ≈  45nm
45nm  *.7 ≈  32nm
32nm  *.7 ≈  22nm
22nm  *.7 ≈  15nm
15nm  *.7 ≈  10nm
10nm  *.7 ≈   7nm
7nm*.7 ≈ 4.9nm

Before 32nm, the process node roughly corresponds to the minimum value of drawn gate length and the channel length used to be lower than the node value considering overlap from source and drain regions on gate area. Digital circuits that are synthesized using standard cells and the height ,width of standard cells are multiple of CPP and MMP as shown below

For 32nm process, different foundries had the value of these pitch around 110-130nm. if a foundry can fit a complete MOSFET device i.e source , channel and drain in one gate pitch, the absolute value of gate length would not matter and the area of the digital IC will scale with the product of metal pitch and metal pitch. So to reduce the area further, it makes sense to reduce the pitches. By scaling metal and gate pitchs, foundries continue to offer process improvements without reducing effective channel length. And with this approach ,the correlation of gate length and the node name became dilute.In the 2009 ITRS, the references to the term ‘technology node’ were eliminated. Also, roughly after this time, the process nodes scaled in a way that could be described as equivalent scaling in which the 3 dimensional device structure was improves or scaled to improve performance. As far as the names of latest process nodes such as 14/10/7 are concerned they are simply a commercial name for a generation process technology, with no relation to gate length, metal pitch or gate pitch.

Now if i say 28nm technology , we have 28nm, 30nm, 35nm, 40nm different gate length options. And the technology node will take the minimum gate length.Every thing  looks good till here but why we need different gate length for a technology node because in some design the minimum timing is met with 30nm gate length and in some other design minimum power is achieved with different gate length.  For 32nm process, different foundries had the value of these pitch around 110-130nm. if a foundry can fit a complete MOSFET device i.e source , channel and drain in one gate pitch, the absolute value of gate length would not matter and the area of the digital IC will scale with the product of metal pitch and metal pitch. So to reduce the area further, it makes sense to reduce the pitches. By scaling metal and gate pitchs, foundries continue to offer process improvements without reducing effective channel length. And with this approach ,the correlation of gate length and the node name became dilute.In the 2009 ITRS, the references to the term ‘technology node’ were eliminated. Also, roughly after this time, the process nodes scaled in a way that could be described as equivalent scaling in which the 3 dimensional device structure was improves or scaled to improve performance. As far as the names of latest process nodes such as 14/10/7 are concerned they are simply a commercial name for a generation process technology, with no relation to gate length, metal pitch or gate pitch.