Why mosfet are replaced by FD-SOI ,Finfet below 28nm technology?

During my internship days at ST Microelectronics, Greater Noida,  I saw a poster which describes about the FDSOI technology. In those days I used to think what is the difference between finfet and FDSOI. In these post we will discuss about why FDSOI or Finfet was required.

Even though we had mosfet, industry is driving towards new technologies like Finfet, Fdsoi. For various reasons industries are forced to design a soc/chip which occupies less area, consumes less power, and also gives better performance, even though all three parameters cannot be achieved at same time. By shrinking the devices(reducing the channel length) we can reduce the area occupied, reduce the power, and increase the performance.
But as we go below 28nm in bulk planar transistors, leakage current increases as a result power consumption increases. Some of the Limitation for  planar transistor that prevent the usage of them below 28nm are.

  • Gate control on the channel is not 100% and this results in higher leakage current. Following are the sources for leakage power
    • Reverse bias p-n junction leakage
    • currentSub threshold leakage current           
    • Tunnel current through the oxide           
    • Gate current due to hot carrier injection           
    • Gate induced drain leakage current           
    • Channel punch through current
  • Device is not truley OFF

To overcome this limitation designer need to make the channel thinner so that gate control over the channel increases.This was the main reason why Finfet and Fdsoi technologies are invented

Finfet
Instead of having a planar transistor with the channel  in the silicon wafer, the channel is created as a thin vertical fin and the gate is wrapped around three sides of the fin. Now gate as more controlled over the channel and leakage power was reduced. Switching speed is more compared to mosfet devices

Fig 1: FinFet

For PMOS
– Mo (4.95 eV)
For NMOS
– Ta (4.25eV)/ Mo stack
-Ta Inter Diffusion in Mo

FD-SOI
These approach was developed by ST Microelectronics. In FD-SOI instead of making the channel area out of the silicon wafer itself, start with an insulator and add a thin layer on top it to form the channel.Then build the planar gate on top of it in normal, along with source and drain. With insulating layer at the back, the channel is thin and like in Finfet case, it is well controlled by the gate. Unlike in planar transistor or mosfet, in FD-SOI can have multiple Vt(threshold voltage) by changing the body bias of the FD-SOI and this is one of the advantages where we can control the Vt of the devices even after  manufacturing it.

Fig 2 : FDSOI

In mosfet the channels are doped but in case of FD-SOI and Finfet the channels are not doped, these eliminates the random dopant fluctuation, which is one of the biggest sources of threshold voltage variability. This undoped channels gives the ability of changing the Vt of the devices(FD-SOI) by changing the back body bias voltage.

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