Digitally Controlled PWM Generator

Design specification
Design and implementation of  architecture of Frequency trigger, Finite State Machine (FSM) for generating the PWM signal ,Pulse Width Modulation.
Input   :  clk,
Input   : [11:0]sin amp
Input   : switch0,fmhigh,fmlow.
Output: [1:0] pwm

Depending upon frequency high(fmhigh), frequency low(fmlow),frequency trigger will generate different  waveforms. By using fsm we design  Pwm model. 

Architecture for the design specification 

Fig 1: FSM
Fig 2: Block diagram

 Manual calculation
PWM is modulation technique used to encode a message into a pulsing signal. In PWM Ton denotes the one time and Toff denotes the off time of signal. Period is the sum of both on and off times and is calculated as shown below.

  Ttotal =Ton +Toff

Duty cycle is calculated as on time to the period and duty is calculated as below

D=Ton /(Ton + Toff)
 D= Ton/Ttotal

PWM Signal when used at a different duty cycles gives a varying voltage at the output. This method is used in various applications like:

  • Switching regulators
  • Led dimmers
  • Audio
  • Analog signal generation
  • Speed control of Motors

The out voltage is calculated by following equations

Vout  = D*Vin
Vout =(Ton /Ttotal)*Vin

  verilog code in next post      

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