Digitally Controlled PWM Generator

Design specification
Design and implementation of  architecture of Frequency trigger, Finite State Machine (FSM) for generating the PWM signal ,Pulse Width Modulation.
Input   :  clk,
Input   : [11:0]sin amp
Input   : switch0,fmhigh,fmlow.
Output: [1:0] pwm

Depending upon frequency high(fmhigh), frequency low(fmlow),frequency trigger will generate different  waveforms. By using fsm we design  Pwm model. 

Architecture for the design specification 

                                                             Fig 1: FSM

                                                       Fig 2: Block diagram

 Manual calculation
PWM is modulation technique used to encode a message into a pulsing signal. In PWM T_on denotes the one time and T_off denotes the off time of signal. Period is the sum of both on and off times and is calculated as shown below.

  T_total =T_on +T_off

Duty cycle is calculated as on time to the period and duty is calculated as below

D=T_on /(T_on + T_off)
 D= T_on/T_total

PWM Signal when used at a different duty cycles gives a varying voltage at the output. This method is used in various applications like:

• Switching regulators
• Led dimmers
• Audio
• Analog signal generation
• Speed control of Motors

The out voltage is calculated by following equations

V_out  = D*V_in
V_out =(T_on /T_total)*V_in

  _{verilog code in next post}