# Why NAND gate is preffered over NOR gate

NAND gates are preferred over NOR gates, because of below factors

• Delay offered by NAND gate is less than NOR gate
• Also NAND gate takes less size.
• Low to high and high to low time are more symmentrical in NAND based design than in NOR based design

Before understanding why NAND gate offers less delay compare to NOR gate, we need to understand the pmos and nmos in circuit level and also different delays.
RC equivalent circuit of nmos and pmos with width k is shown in fig 1.

Lets us analyse the rc model of inverter (with kn=1 and kp=2) which is connected to another inverter of same kn and kp value as shown in below fig 2.

Have you noticed width of pmos(kp) is twice the nmos(kn), what could be the reason?

In inverter nmos and pmos are connected in series and therefore current through the pmos must be equal to nmos. As mobility of holes are less and offers more resistance, thus to increase the flow of holes channel width of pmos is made twice that of nmos channel width. The elmore delay of the previous ciruit is show below and from this circuit we can calculate all the delays of circuit.

Delay of any device can expressed as sum of parasitic delay and effort delay/stage effort that depends on complexity and fan-out of the gate
d=p+f
p————–is the delay of the gate/device when no load is attached.
f—————is the effort delay
f=gh
The complexity is represented by the logical effort, g and this defined as ratio of input capacitance of a gate to the input capacitance of an inverter that as same drive strength (i.e. delivers same current).

Electrical effort is denoted by h, If the load does not contain identical copies of the gate, the electrical effort can be computed as