T3 Violation in DFT

Pattern are generated on the DFT logic inserted design, before generating the pattern the tool will check for certain rules and reports DRC violations as a part of ATPG flow. One of the rule is Tracing of scan chains from output pin to scan input pin, if the tool is unable to trace back, it will through a Trace (T rule) violation.

When the shift procedure failed to create a path from scan chain output pin back to scan chain input pin, then tool reports a trace violation (T-3). In this case engineer as to take care to properly constrain the input pins which are responsible for activating the DFT logic in the design. T3 violation can occur due to many reasons, few of them are explained below

Case I:

In this case as shown below after tracing till 10^th scan cell, chain tracing was blocked due the BLACK BOX present in the scan chain path and reports T3 violation by tool.

This can be solved by loading the BLACK BOX definition during the setup phase, which will help the tool to trace the chain from scan_out pin to scan_in pin  

Case II:

In this case shown below, there is a trace blockage in scan chain at 2^nd cell as there is no toggling activity of clock. When we trace back the clock pin, we can see that clock is coming from a mux and select line for mux is x.

This can be solved by making clock of FF3 to toggle, which makes the input D to appear at output pin of FF3. This makes the select line to low (i.e. is 0) and the D0 pin will be selected, which is toggling.

We have to make the clk1 pin to toggle, constraint the D pin of FF3 to 1 and we need to inform the tool about the constraints by following commands in a do file.
add_clock 0 clk1
add_input_constraint D –c0

We also need to modify the test procedure to pulse the clk1.
Template gen_tp =
offstate “clk1” 0 ;
force_pi 0 ;
 measure_po  100 ;
pulse clk1 200 100 ;
period 400 ;
end;

procedure test_setup =
temeplate gen_tp ;
cycle =
force D 0 ;
pulse clk1 ;
end ;
end;

CHISEL

Chisel (Constructing Hardware in a Scala Embedded Language)

Is a new hardware language which made open source by UC Berkeley. Chisel supports the advance hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel provides the flexibility of concepts like object orientation, functional programming, parameterized types and type inference over the VHDL or Verilog hardware languages. Chisel adds hardware construction primitives to the scala programming language, providing designers with power of a modern programming language to write complex, prameterizable circuit generators that produce sythesizble Verilog. With single chisel code, we can generate a high-speed C++ based cycle –accurate software simulator, or low-level Verilog design for ASIC or FPGA for synthesis, place and route.

Chisel is powered by FIRRTL (highly parameterized generators and layered domain-specific hardware languages), a hardware complier that performs optimization of chisel-generated circuits.
Steps involved to generate the Verilog from chisel code

1. The Chisel stage/Font-end compiles chisel to a circuit intermediate representation called FIRRTL(highly parameterized generators and layered domain-specific hardware languages
2. FIRRTL stage/ mid-end then optimizes FIRRTL and then applies user custom transformations
3. Finally the Verilog stage/Backend generated the Verilog based on the optimized FIRRTL.

Utilisation Factor

Utilization factor gives us information how much area must be occupied by the standard cell. As we increase the utilization factor , total area of the chip or block will be decreased. Let us discuss how the total area decreases and total area was

Total Core Area = area occupied by macros+area occupied by standard cell+ empty area

UF  is defined as (area occupied by the standard cell)/(Total Core Are) and the UF is varied from .3 to .8 . In  industry mostly they will go with utilization factor of 0.7 -0.8

Assume that standard cell occupy 80mm area, all macros in the design occupy 30mm area

• Utilization Factor be 70% means in the core area there should be 30% of free space for future use.
  std. cell area =80mm
  All macros area = 30mm
  Free space area =35 mm
  Total Core Area= 80+30+35 =145mm
  
  And this explained properly in below figure.

• Utilization Factor be 80% means in the core area there should be 20% of free space for future use
  std. cell area =80mm
  All macros area = 30mm
  Free space area =20 mm
  Total Core Area= 80+30+20 = 130mm

we can observe that area of the core decreases if we increase the utilization factor of the block or design

Full Adder

For three bit additions, full adder is used. First step in designing the full Adder circuit is to have truth table. Before that let see the binary addition rules.

Truth Table for Full Adder

Using the k-map, we can get the optimised Boolean expression for sum and carry.
Boolean expression for sum

Boolean Expression for carry

From the above booleaan expression , we can Implement of sum and carry as shown below