Pattern are generated on the DFT logic inserted design, before generating the pattern the tool will check for certain rules and reports DRC violations as a part of ATPG flow. One of the rule is Tracing of scan chains from output pin to scan input pin, if the tool is unable to trace back, it will through a Trace (T rule) violation.
When the shift procedure failed to create a path from scan chain output pin back to scan chain input pin, then tool reports a trace violation (T-3). In this case engineer as to take care to properly constrain the input pins which are responsible for activating the DFT logic in the design. T3 violation can occur due to many reasons, few of them are explained below
In this case as shown below after tracing till 10th scan cell, chain tracing was blocked due the BLACK BOX present in the scan chain path and reports T3 violation by tool.
This can be solved by loading the BLACK BOX definition during the setup phase, which will help the tool to trace the chain from scan_out pin to scan_in pin
In this case shown below, there is a trace blockage in scan chain at 2nd cell as there is no toggling activity of clock. When we trace back the clock pin, we can see that clock is coming from a mux and select line for mux is x.
This can be solved by making clock of FF3 to toggle, which makes the input D to appear at output pin of FF3. This makes the select line to low (i.e. is 0) and the D0 pin will be selected, which is toggling.
We have to make the clk1 pin to toggle, constraint the D pin of FF3 to 1 and we need to inform the tool about the constraints by following commands in a do file.
add_clock 0 clk1
add_input_constraint D –c0
We also need to modify the test procedure to pulse the clk1.
Template gen_tp =
offstate “clk1” 0 ;
force_pi 0 ;
measure_po 100 ;
pulse clk1 200 100 ;
period 400 ;
procedure test_setup =
temeplate gen_tp ;
force D 0 ;
pulse clk1 ;