Design for Testability circuit is used for controllability and observability of the design. The test logic is inserted in to the main core logic for testing the chip once it is manufactured. Types of DFT logic are
- Logic BIST
Build in self-test is inserted into the core logic design. This circuit is used to test the core logic.
Memory build in self-test is carried on the memory elements and this logic is used for testing memories
- Boundary Scan
In the board level Boundary Scan circuitry provides the access to the inputs and output ports of the chips. This circuitry not only does board level testing, it can also do circuit level such as BIST or internal scan and it can test board interconnection. To control all these operation, TAP controller was used.