does knowlege on Location of MEMORIES was important during mbist implementation

MBIST( Memory Built In Self Test) is implemented to test memories in the design for different types of faults. MBIST contains the processor and wrapper which will be wrapped arround the memories.The MBIST processor controlls the wrapper and generates various control signals during the memory testing. A design may have multiple processors depending on the number of memories, memory size, power, frequency and memory placement.

Memories which are placed near by are grouped together and controlled by single processor. Thereofore, we need the memory placement info to group the memories under a controller and this info was given to the DFT team in the form of DEF and floorplan snapshot. This info will be given by PD/PNR team.

What happens if memories are not grouped properly?
If memories are not grouped properly according to their physical location i.e memories under same processors are sitting at different corners. This will lead to MBIST logic spreading, which impacts on MBIST timing during the STA due to long paths or increase in congestion due to lots of criss-cross while implementing the PNR and also increases the unneccesary power consumtption.

CHISEL:multiplexer

A multiplexer is a circuit which selects between the input signals depending on select signal. In basic form of multipexer (2:1 mux) selects between two signals. Below fig represents the 2:1 multiplexer , depending upon the sel signal y will represent the input signal a or b

A multiplexer can be designed using logic gates. As the multiplexer is used more frequently in digital desgin, chisel provides the function called MUX

val results = Mux(sel , a, b)

where a is selected when sel is true, otherwise b is selected, type of sel is a chisel Bool. The inputs a and b can be any chisel base type or aggregate (bundlers or vectors) as long as they are same type

A Bundle to group signals of different types. A Vec to represents an indexable collection of signals of the same type

Techniques to reduce the patterns count without losing coverage

During the DFT validation patterns are used which are generated during ATPG stage, even these patterns(in Still, wgl format) are used to test a chip on ATE. As there is limitation on memory of the ATE, size of the patterns generated must be with in the memory limit of ATE. Thus we have to reduce the patterns count/pattern volume for a design without losing the coverage. Few of the technique are

• For pattern reduction, First step is chain balancing. During scan insertion scan chains present in the design must be balanced(of equal length), so that tool will insert the less dummy patterns for reaching a required flip flop.
• we can also include compression on the chains. This means if we are having the compression factor of 2 then your 1 scan chain will get divided into 2 inside the device reducing your chain length (flops per scan chain), thus less patterns are required.

compression ratio:
The compression ratio in DFT used to reduce the TESTER Application time and TESTER data volume(size of pattern).