Different ways of Digital design representation

A digital design can be represented at various levels from three different angles

  • Behavioral
  • Structural
  • Physical

This can be represented by Y chart

Y-chart

Behavioral Representation

  • Specifies how a particular should respond to a given set of inputs
  • May be specified by
    -Boolean Equations
    -Tables of input and output values
    -Algorithms written in standard HLL like C/C++
    -Algoriths written in special HDL like verilog or VHDL or CHISEL

Example:

———————————–An Algorithm level of description of carry(Cy)———————————-
module carry (cy, a,b,c);
input a,b,c;
output cy;
assign cy = (a&b)|(a&c)|(b&c);
endmodule

——————————Boolean behavioral specification for carry (cy)————————————
primitive carry (cy,a b,c);
input a,b,c;
output cy;
table
// a b c : cy
   1 1 ? : 1 ;
   1 ? 1 : 1 ;
   ? 1 1 : 1 ;
   0 0 ? : 0 ;
   0 ? 0 : 0 ;
   ? 0 0 : 0 ;
endtable
endprimitive

Structural Representation

  • Specifies how components are interconnected
  • In general, the description is a list of modules and their interconnects
    – called Netlist
    – can be represented at various levels
  • At Structural Level, levels of abstraction are:
    – The module (functional) level
    – The Gate level
    – The switch level
    – The circuit level

Example:
——————————————–Structural Representation—————————————–
module carry (cy , a, b, c);
input a, b, c;
output cy;
wire w1,w2,w3;
  and g1 (w1, a, b);
  and g2 (w2, a, c);
  and g3 (w3, b, c);
  or g4 (cy, w1,w2,w3);
endodule

Physical Representation

  • The lowest level of physical specification
    – Photo-mask information required by various processing steps in the fabrication process.
  • At the module level, the physical layout for the adder may be defined by a rectangle or polygon, and collection of ports

Example:
———————————————–Physical representation————————————————-
A possible (partial) physical description of 4 bit adder

module adder4 ;
input [3:0] a,b;
input c;
output [3:0] s;
output cy;
boundary [0 0 130 500];
port x[0] aluminum width = 1 origin = [0,35];
port y[0] aluminum width = 1 origin = [0,85];
port c polysilicon width = 2 origin = [70,0];
port s[0] aluminum width = 1 origin = [120,65];

add a0 orgin =[0 , 0];
add a1 orgin =[0 ,120];
endmodule

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