By using full adder, a single 1-bit binary adders can be constructed from basic logic gates as shown below But what if we wanted to
In digital systems counter is plays a main role. Counters are used to keep a track of events , time intervals and no of interrupts
Scan cell is one of the DFT technique , to test the sequential circuits in the Asic/Soc design. Normal D flip flop are converted to
Scan chain reordering is an optimization technique to ensure scan chains are connected in more efficient way – based upon the placement of the flip-flops.