By using full adder, a single 1-bit binary adders can be constructed from basic logic gates as shown below
But what if we wanted to add together two n-bit numbers, then n number of 1-bit full adders need to be connected or “cascaded” together to produce a adder known as a Ripple Carry Adder.
Ripple carry adder is simply “n“ number of 1-bit full adders cascaded together with full adder representing a single weighted column in a long binary addition. It is called a ripple carry adder because the carry signals produce a “ripple” effect through the binary adder from LSB to MSB.
Let us consider a three bit full adders to “add” together two 3-bit numbers, the two outputs of the first full adder will provide the first place digit sum (S) of the addition plus a carry-out bit that acts as the carry-in digit of the next binary adder. The second binary adder in the chain also produces a summed output (the 2nd bit) plus another carry-out bit and we can keep adding more full adders to the combination to add larger numbers, linking the carry bit output from the first full binary adder to the next full adder, and so forth. An example of a 3-bit adder is given below.
Let us consider A =4 , B=3, sum of A and B will be 7. In binary addition
There will be a overflow ,If the sum was greater than or equal to 2n one of the disadvantage in this adder. Let us consider A =4 , B=4, Sum of A and B will be 8 which is equal to 23 and we will have a overflow .
There two main disadvantages in ripple carry adder
- Propagation delay:
if inputs A and B changes, the sum at its output will not be valid until any carry-input has “rippled” through every full adder in the chain because the MSB of the sum has to wait for any changes from the carry input of the LSB. Consequently, there will be a finite delay before the output of the adder responds to any change in its inputs resulting in a accumulated/propagation delay. This delay can be neglected for 4 to 8 bits but we cannot neglect the delay for higher bits like 32 bits and more.
- Over flow:
Overflow occurs when the two n bit numbers add together whose sum is greater than or equal to 2n
To reduce the propagation delay of carry_in we can use Carry Look Ahead Binary Adder