CHISEL : Bundle

In Chisel provides two constructs to group related signals

  • A Bundle to group signals of different type.
  • A Vec represents the collection of signal of same type.

A chisel Bundle groups several signals. The entire bundle can be accessed or individual field can be accessed by their names. User or Designer can define a bundle(collections of signals) by definnig a class which extends Bundle and list the fields as vals within the constructor block

class vlsispace() extends Bundle {
val vlsi = UInt(32.W)
val space = Bool()

To access the bundle in following way
val vs = Wire(new vlsispace())
vs.vlsi := 124.U := false.B

val a =

By using the dot we can access the field of the particular constructor, which is commonly used in object oriented programming. A Bundle is similar to struct in C , a record in VHDL or struct in system verilog. A bundle can be referred as a whole as follows

val channel = vs

A bundle may as well contain a vector:

class BundleVec extends Bundle {
val vs = UInt(8.U)
val vector = Vec(4 , UInt(4,W))

When we want a register of a bundle type that needs a reset value, we first wire of that bundle and define the values for the bundle elements and then passing the bundle to RegInit:

val initval = Wire( new vlsispcae())
initval.vlsi := 1.U := true.B

val channelreg = RegInt(initval)

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