Gate delays

Gate Delays

In Verilog, a designer can specify the gate delays in verilog code. This helps the designer to get a real time behavior of the logic circuit.

Rise delay: It is equal to the time taken by a gate output transition to 1, from another value 0, x, or z.

Fall delay: It is equal to the time taken by a gate output transition to 0, from another value 1, x, or z.

Turn-off delay: It is equal to the time taken by a gate output transition to high impedance state, from another value 1, x, or z.

• If the gate output changes to x, the minimum of the three delays is considered.
• If only one delay is specified, it is used for all delays.
• If two values are specified, they are considered as rise, and fall delays.
• If three values are specified, they are considered as rise, fall, and turn-off delays.
• The default value of all delays is zero.

and #(5) and_1 (out, in0, in1);
// All delay values are 5 time units.

and #(3,4,5) nand_1 (out, in0, in1);
// rise delay = 3, fall delay = 4, and turn-off delay = 5.

and #(3,4) or_1 (out, in0, in1);
// rise delay = 3, fall delay = 4, and turn-off delay = min(3,4) = 3.

There is another way of specifying delay times in verilog. Min:Typ:Max values for each delay. This helps designer to have a much better real time experience of design simulation, as in real time logic circuits the delays are not constant. The user can choose one of the delay values using +maxdelays, +typdelays, and +mindelays at run time. The typical value is the default value.

and #(4:5:6) and_1 (out, in0, in1);
// For all delay values: Min=4, Typ=5, Max=6.

and #(3:4:5,4:5:6,5:6:7) nand_1 (out, in0, in1);
// rise delay: Min=3, Typ=4, Max=5, fall delay: Min=4, Typ=5, Max=6, turn-off delay: Min=5, Typ=6, Max=7.

In the above example, if the designer chooses typical values, then rise delay = 4, fall delay = 5, turn-off delay = 6.

Basics : Data Types III

Vectors

Vectors can be a net or reg data types. They are declared as [high:low] or [low:high], but the left number is always the MSB of the vector.

wire [7:0] vs; // vs[7] is the MSB.
reg [0:15] vs_1; // vs_1[15] is the MSB.

In the above examples: If it is written as vs[5:2], it is the part of the entire vector which contains 4 bits in order: vs[5], vs[4], vs[3], vs[2].

Similarly vs_1[0:7], means the first half part of the vecotr vs_.1
Vector parts can also be specified in a different way:
vector_name[start_bit+:width] : part-select increments from start_bit in above example: vs_1[0:7] is same as vs_1[0+:8].

vector_name[start_bit-:width] : part-select decrements from start_bit in above example: vs[5:2] is same as vs[5-:4].

Arrays

Arrays of reg, integer, real, time, and vectors are allowed. Arrays are declared as follows:

reg vs1[0:7];
real vs3[15:0];
wire [0:3] vs4[7:0]; // Array of vector
integer vs5[0:3][6:0]; // Double dimensional array

Strings

Strings are register data types. For storing a character, we need a 8-bit register data type. So if you want to create string variable of length n. The string should be declared as register data type of length n*8.

reg [8*8-1:0] vs_1; // vs_1 is a string of length 8.

Time Data Types

Time data type is declared using the keyword time. These are generally used to store simulation time. In general it is 64-bit long.

time vs_1;
Vs_1 = $time; // assigns current simulation time to vs_1.

Basics : Data types II

Integers

Integer is a register data type of 32 bits. The only difference of declaring it as integer is that, it becomes a signed value. When you declare it as a 32 bit register (array) it is an unsigned value. It is declared using the keyword integer.

Real Number

Real number can be declared using the keyword real. They can be assigned values as follows:
real VS;

VS = 1.234; // Decimal notation.
VS = 3e4; // Scientific notation.

Parameter

Parameters are the constants that can be declared using the keyword parameter. Parameters are in general used for customization of a design. Parameters are declared as follows:

parameter vs = 123; // vs is a constant with value 123.

Keyword defparam can be used to change a parameter value at module instantiation. Keyword localparam is usedd to declare local parameters, this is used when their value should not be changed.

Basics : Data Types I

Value Set

The Verilog HDL value set consists of four basic values:

• 0 – represents a logic zero, or a false condition.
• 1 – represents a logic one, or a true condition.
• x – represents an unknown logic value.
• z – represents a high-impedance state.

The values 0 and 1 are logical complements of one another. Almost all of the data types in the Verilog HDL store all four basic values.

Nets

Nets are used to make connections between hardware elements. Nets simply reflect the value at one end(head) to the other end(tail). It means the value they carry is continuously driven by the output of a hardware element to which they are connected to. Nets are generally declared using the keyword wire. The default value of net (wire) is z. If a net has no driver, then its value is z.

Register

Registers are data storage elements. They hold the value until they are replaced by some other value. Register doesn’t need a driver, they can be changed at anytime in a simulation. Registers are generally declared with the keyword reg. Its default value is x. Register data types should not be confused with hardware registers, these are simply variables.