Gate Delays In Verilog, a designer can specify the gate delays in verilog code. This helps the designer to get a real time behavior of
Vectors Vectors can be a net or reg data types. They are declared as [high:low] or [low:high], but the left number is always the MSB
Integers Integer is a register data type of 32 bits. The only difference of declaring it as integer is that, it becomes a signed value.
Value Set The Verilog HDL value set consists of four basic values: 0 – represents a logic zero, or a false condition. 1 – represents