The Verilog HDL value set consists of four basic values:
- 0 – represents a logic zero, or a false condition.
- 1 – represents a logic one, or a true condition.
- x – represents an unknown logic value.
- z – represents a high-impedance state.
The values 0 and 1 are logical complements of one another. Almost all of the data types in the Verilog HDL store all four basic values.
Nets are used to make connections between hardware elements. Nets simply reflect the value at one end(head) to the other end(tail). It means the value they carry is continuously driven by the output of a hardware element to which they are connected to. Nets are generally declared using the keyword wire. The default value of net (wire) is z. If a net has no driver, then its value is z.
Registers are data storage elements. They hold the value until they are replaced by some other value. Register doesn’t need a driver, they can be changed at anytime in a simulation. Registers are generally declared with the keyword reg. Its default value is x. Register data types should not be confused with hardware registers, these are simply variables.