What is Verilog

 What is Verilog?

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. 

A brief history 

Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway  Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu  Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil   Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally  acquired by Cadence Design Systems, San Jose, CA in 1989. 

Verilog was invented as simulation language. Use of Verilog for synthesis was a complete  afterthought 

Cadence Design Systems decided to open the language to the public in 1990, and thus OVI  (Open Verilog International) was born. Till that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog  simulators. The first of these came to market in 1992, and now there are mature Verilog  simulators available from several sources. 

As a result, the Verilog market has grown substantially. The market for Verilog related tools in  1994 was well over $75m, making it the most commercially significant hardware description language on the market. 

An IEEE working group was established in 1993 under the Design Automation Sub-Committee  to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.

The Verilog Standard was revised in 2001 and it became IEEE Standard 1364-2001

WHAT IS SYNTHESIS IN DIGITAL DESIGN

 Synthesis

Synthesis: It is a process to map and optimizing higher level HDL description to technology cells (gates, flip flops etc.)

Synthesis Flow Diagram:

HDL Description: This is description of design in Verilog. One has to use subset of constructs as synthesis tools does not support all of them.

Technology Library: This file contains functional description and other information related to area and speed for all the cells of particular technology.

Here "technology" means information about particular process for particular vendor. For example Company X, Standard Cell, 0.18 micron, Y Process, Z Type.

Constraints: This optional file contains information about physical expectations from design. For example speed and area.

Netlist: A netlist is a text file description of a physical connection of components.

Reports: This optional output file contains physical performance of design in terms of speed and area.

Schematic: Some tools provide the facility to view netlist in terms of schematics for better understanding of design and to match the results with the expectations.

Simple example:
Following trivial example explains the Synthesis process. In this example only always procedural statement is used.

module test (out, in1, in2); // behavioral description
  input in1, in2;
  output out;
  reg out;
  reg temp;                 // temporary register

  always@(in1 or in2) begin
    temp = ~in2;
    out = ~in1 ^ temp;  // I am trying to have exor with inverted 
  end                   // inputs
endmodule

after synthesis one gets following "netlist" in verilog. Note that XOR2 is module picked up from technology library. It will be different for different libraries.

module add ( out , in1 , in2 );  // netlist

    output out ;
    input in1 ;
    input in2 ;

    XOR2   instance_name (.Y (out ),.A (in1 ),.B (in2 ) );

endmodule

VERILOG CODE FOR D FLIP FLOP

The Verilog beginners need examples of simple building blocks to learn coding techniques. Now  we will go through different implementation of D FLIP FLOP

=========================================================================

1.Simple D FLIP FLOP 

module dff (data, clock, q);
    // port list
    input   data, clock;
    output  q;

    // reg / wire declaration for outputs / inouts     
    reg     q;

    // logic begins here
    always @(posedge clock) 
        q <= data;
endmodule

========================================================================

2. D Type Flip-flop with asynchronous reset

module dff_async (data, clock, reset, q);

    // port list
    input   data, clock, reset;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // reg / wire declaration for internal signals

    // logic begins here
    always @(posedge clock or negedge reset)
        if(reset == 1'b0)
            q <= 1'b0;
        else 
            q <= data;
endmodule

=======================================================================

3. D Type Flip-flop with Synchronous reset

module dff_sync (data, clock, reset, q);
    // port list
    input   data, clock, reset;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // reg / wire declaration for internal signals

    // logic begins here
    always @(posedge clock) 
        if(reset == 1'b0)
            q <= 1'b0;
        else 
            q <= data;
endmodule

================================================================================

4.D Type Flip-flop with asynchronous reset and clock enable

module dff_cke (data, clock, reset, cke, q);
    // port list
    input   data, clock, reset, cke;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // logic begins here
    always @(posedge clock or negedge reset) 
        if (reset == 0)
            q <= 1'b0;
        else if (cke == 1'b1)
            q <= data;
endmodule

Vlsi Design Styles in Digital Design

Digital Design can be implemented by various design styles. And depending on the market requirement different design styles are used.

• Programmable Logic Design
  • Field Programmable Gate Array (FPGA)
  • Gate Array
• Standard Cell (semi custom design)
• Full Custom Design

• Field Programmable Gate Array (FPGA):
  • Using VHDL or verilog
  • Implementation
    • Placement and Routing
    • BitStream Generation
    • Analyse timing, view layout, simulations etc
• Gate Array: Gate Array design implementation is done with metal design and processing. The implementation requires two-step manufacturing process
  • First phase, which is based on standard masks, results in an array of uncommitted transistors on each GA chips
  • These uncommitted chips can be customized later, which is completed by defining the metal interconnects between the transistor of the array
  • In this chip utilization factor is higher than that of FPGA
  • Chip speed is higher
• Standard Cell or Semi Custom Design:
  • The standard-cells based design is often called semi custom design.
  • The cells are pre-designed for general use and the same cells are utilized in many different chip designs. 
• Full Custom Design
• Full custom design involves creating IC where each individual transistors architecture and interconnections are specified. Designers manually place transistors, resistors,capacitors and other components at the transistor level

STANDARD CELLS IN DIGITAL DESIGN/VLSI

Standard cell are well defined cells which are used in Digital Design more frequently. To name few AND, NOR, NAND, XOR ,etc belongs to standard cell family. All the standard cells from one library will have equal drive strength  and  equal height. Standard cell Architecture is defined based on  cell height which is determined on the basis of the number of trackes , beta ratio, pitch and transistor widths. To attain the similarity amoung the cells and aboid the alignment issues ,standard cells are designed with fixed height

The height of a standard cell can be calculated by considering number of tracks required for power rail, ground rail, I/O pins and routing. Often the standard cells are available in single height and double height. The Double height cells are the high density cells and are used for ultra high speed operations 

STANDARD CELL DESIGN METHODOLOGY

• VDD and GND should be of same height and parallel. Both the power rails used metal M1
• make sure within the cell all the PMOS should occupy top and all NMOS should occupy bottom of the Layout
• Preferred Practice:  Diffusion layer for all the transistor in a row
• All the gates include the gate and substrate

 Layout for any schematic can be drawn in many ways. Layout of INVERTER can be drawn in two different ways.

In the Fig 2 was preferred layout as all the PMOS will be in one level and all the NOMS will be at one level, and also the poly gates are drawn vertical and these are common to nmos and pmos transistors. 

One more layout example with NAND GATE

There are many reasons for choosing the FIG 2 and FIG 3 as most preferred Layout

• Save the Design Area: Both the nwell and pwell are in the same level for all the standard cell, so make a common well which saves lots of areas 
• Easy Placement for APR tool: All the standard cells have the same height and easily can be fit into the standard cell row so make it easy for APR (Automatic Place and Route) to place them. They also have power rails in the same location for all the standard cells, so power rails can also be abutted easily 
• Easy to Route: All the pins of standard cells are in the intersection of horizontal and vertical tracks, So it becomes easy to route them by the APR tool .