WHAT IS SYNTHESIS IN DIGITAL DESIGN

 Synthesis

Synthesis: It is a process to map and optimizing higher level HDL description to technology cells (gates, flip flops etc.)

Synthesis Flow Diagram:

HDL Description: This is description of design in Verilog. One has to use subset of constructs as synthesis tools does not support all of them.

Technology Library: This file contains functional description and other information related to area and speed for all the cells of particular technology.

Here "technology" means information about particular process for particular vendor. For example Company X, Standard Cell, 0.18 micron, Y Process, Z Type.

Constraints: This optional file contains information about physical expectations from design. For example speed and area.

Netlist: A netlist is a text file description of a physical connection of components.

Reports: This optional output file contains physical performance of design in terms of speed and area.

Schematic: Some tools provide the facility to view netlist in terms of schematics for better understanding of design and to match the results with the expectations.

Simple example:
Following trivial example explains the Synthesis process. In this example only always procedural statement is used.

module test (out, in1, in2); // behavioral description
  input in1, in2;
  output out;
  reg out;
  reg temp;                 // temporary register

  always@(in1 or in2) begin
    temp = ~in2;
    out = ~in1 ^ temp;  // I am trying to have exor with inverted 
  end                   // inputs
endmodule

after synthesis one gets following "netlist" in verilog. Note that XOR2 is module picked up from technology library. It will be different for different libraries.

module add ( out , in1 , in2 );  // netlist

    output out ;
    input in1 ;
    input in2 ;

    XOR2   instance_name (.Y (out ),.A (in1 ),.B (in2 ) );

endmodule