The Verilog beginners need examples of simple building blocks to learn coding techniques. Now we will go through different implementation of D FLIP FLOP
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1.Simple D FLIP FLOP
module dff (data, clock, q);
// port list
input data, clock;
output q;
// reg / wire declaration for outputs / inouts
reg q;
// logic begins here
always @(posedge clock)
q <= data;
endmodule
========================================================================2. D Type Flip-flop with asynchronous reset
module dff_async (data, clock, reset, q);
// port list
input data, clock, reset;
output q;
// reg / wire declaration for outputs / inouts
reg q;
// reg / wire declaration for internal signals
// logic begins here
always @(posedge clock or negedge reset)
if(reset == 1'b0)
q <= 1'b0;
else
q <= data;
endmodule
3. D Type Flip-flop with Synchronous reset
module dff_sync (data, clock, reset, q);
// port list
input data, clock, reset;
output q;
// reg / wire declaration for outputs / inouts
reg q;
// reg / wire declaration for internal signals
// logic begins here
always @(posedge clock)
if(reset == 1'b0)
q <= 1'b0;
else
q <= data;
endmodule
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4.D Type Flip-flop with asynchronous reset and clock enable
module dff_cke (data, clock, reset, cke, q);
// port list
input data, clock, reset, cke;
output q;
// reg / wire declaration for outputs / inouts
reg q;
// logic begins here
always @(posedge clock or negedge reset)
if (reset == 0)
q <= 1'b0;
else if (cke == 1'b1)
q <= data;
endmodule
