Tap Cells (Well Taps) : These library cells
connect the power and ground connections to the substrate and nwells,
respectively.
By placing well taps at regular
intervals throughout the design, the nwell potential is held constant for
proper electrical functioning. The placer places the cells in accordance with
the specified distances and automatically snaps them to legal positions (which
are the core sites).
All the cells discussed in these post are called Physical only cells, as these cells are not important with respect to Funtional Design. These were invented to Complete the Design properly. These cells does not have any timing constains. There are different types of physical cells. Let us see the usage of different cells
TIE CELLS: Tie High and Tie Low cells are used to connect the gate of the transistor to either power or ground. In Lower technology nodes, if the gate is connected to power/ground the transistor might be turned on/off dure to power or ground bounce. These cells are part of standard cell library. The cells which required Vdd connected to Tie high cells. The cells which require Vss/Gnd connected to Tie low cells. These cells are basically present in the ".lib"
- Floating nets or unused nets need to be tied with some constant value (0 or 1), can be achieved using Tie cells
- Using connect_tie_cells command, we can inser a tie cell in the design during the PNR
TIE HIGH CELLS:
Using these cells we directly connect the VDD to the gate transistor, now we connect the O/P of these cells to the transistor gate if any fluctuations in VDD due to ESD then PMOS circuit pull it back to stable state. PMOS should be ON always, the I/P of the PMOS transistor is coming from the O/P of NMOS transistor and For NOMS gate and drain are shorted and NMOS will be in saturation mode which act as a pull down circuit and always gives a low voltage at the gate of PMOS. Now PMOS will on and gives stable high output and this output is connected to the gate of transistor
ENDCAP CELL: These Library cells do not have signal connectivity. They connect only to power and ground rails once power rails created in design. They also ensure that gaps do not occur between the well and implant layers. This prevents DRC violations by satisfying well tie off requirements for the core rows. Each end of the core row, left and right can have only one ENDCAP cell
Hower you can specify a list of different END CAPS for inserting horizontal ENDACP lines, which terminate the top and bottom boundaries of object such as macros. A core row can be fragmented (contains gaps), since row donot intersect objects such as power domains. For this, the tool places ENDCAP cells on both ends of the unfragmented segment.
- To Protect the gate of a standard cell placed near the boundary from damage during manufacturing
- To Avoid the base layer DRC(Nwell and Implant Layer) at the boundary
- To make the proper alignment with other block
- Some standard cell library has END CAP cell which serve as Decap cell as well
DeCAP CELLS: These are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR Drop. Dynamic IR Drop happens at the active edge of the clock at which a high % of sequential and Digital elements switch . Due to this simultaneous switching a high current is drawn from the power grid for a small duration. if the power source is far away from a flop, then there are high chances of this flop to move into metastable state due to IR Drop. To overcome this DECAPS are added. At the active edge of clock when the current requirement is high, these DECAPS discharges and provide boost to the power grid. One major disadvantage in usage of DECAPS is that these add leakage current in the circuit. DECAPS are placed as fillers. The closer they are to the flops, the better it is.
DeCAP Cells are typically poly gate transistors where source and drain are connected to the ground rail, and gate is connected to the power rail
When there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are DECAP cells placed in the Design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open
One drawback of DECAP cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore , is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R & L, the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would cause a trouble, since both the VDD and GND will be oscillating. Few Design were failed because the DECAP cells placed near high activity clock buffers. Most recommended option is a decap optimazation flow where the tool will study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into a account to ensure resonance frequency is not hit
