scan cell, scan chain

Scan cell is one of the DFT technique , to test the sequential circuits in the Asic/Soc design. Normal D flip flop are converted to scan flip flop, if the tool meets the following criteria

• Clock of the flip flop must be controllable
• The set/reset of the flops must be inactive during the shift mode.

Once the all the flops in the design meet the above two rules the tool will convert the d flops to scan flops by adding a mux as shown in figure above. Then the tools will stitch the scan cells into a scan chain according to the design requirements.

When Scan Enable is 0 (SE=0), all the scan chains in the design will be disconnected and the flops are connected to comb. logic

When Scan Enable is 1 (SE=1) , combinational logic will be bypassed and all scan cells will be connected to form a scan chain

When SE=1 , patterns are loaded to the scan chains and the data from the comb logic are captured when SE=0

scan chain REORDERING , why it is required

Scan chain reordering is an optimization technique to ensure scan chains are connected in more efficient way – based upon the placement of the flip-flops. At initial stage , we donot have the placement information, so we just stitch the flops register by register. The tools will stitch the flops randomly to form a scan chain before placement. For proper understanding flops are numbered and two scan chains are stitched in the screen shot shown below.

But after placement it might be possible that the two flops stitched at initial stage of a different block sits far from each other when the placement is done. So if we keep the same scan chain order, we will face the placement congestion and timing congestion and more routing resources are required.

We can see from above screenshot, depending on the timing and placement congestion flops are placed at different locations when compared to before placement figure. This results in usage of more resources, space congestion increases and also timing violations. By reordering the scan cells in the scan chain we can reduce the congestion

In order to avoid the congestion before placement we have to follow the below steps

• Disconnect the scan chain in the designing.
• Based on the timing and congestion the tool optimizes the standard cells
• Once the placement was done, reordering of scan chains are done based on the timing and placement congestion in design by maintaining the same number of scan cells .

SCANDEF file contains the scan chain information of the design and this file need to be read during PnR.

Untestable faults in DFT

Faults list in design are categorized into sub categories. Faults class are mainly divided into

• Testable(TE)–> Faults can be tested by some patterns.
• Untestable(UT)–> Faults foe which no pattern exits to detect the faults

Untestable Faults: Are the faults for which no pattern exit to either detect or possible detect them. These faults cannot cause any functional failures. And so the tools excludes them while calculating the test coverage. Types of Untestable faults are

• Unused (UU)
• Tied (TI)
• Blocked(BL)
• Redundant Faults (RE)

• Unused (UU)
  • Any floating pins not used in the design come under UU faults
  • The unused faults class includes all the faults on circuit unconnected to any observation point

• Tied (TI)
  • This faults includes faults on gates where the point of the faults is tied to a value identical to the fault stuck value

• Blocked (BL)
  • Due to tied logic in the design few faults are blocked and these are categories into Blocked faults. By adding the observable test point we can increase the coverage report.

• Redundant (RE)
  • The faults which are undetectable by the tool by any pattern , are classified as redundant faults

Fault Class Hierarchies in DFT

Faults list in design are categorized into sub categories. Faults class are mainly divided into

• Testable(TE)–> Faults can be tested by some patterns.
• Untestable(UT)–> Faults foe which no pattern exits to detect the faults

• Testable Faults: There are four sub category under TE.
  • DETECTED(DT)
  • POSDET(PD)
  • ATPG UNTESTABLE(AU)
  • UNDETETED(UD)

• Detected(DT): The Faults which are detected during the ATPG process are categories under DT
  • det_simulation(DS): The faults detected when the tools performs simulation
  • det_implication(DI): The faults detected when the tool performs learning analysis
• POSDET(PD): The Possible detected, faults includes all the faults that fault simulation identifies as possible detected
  • posdet_testable(PT): Potentially detectable posdet faults.With higher abort limit we can reduce the number of these faults
  • posdet_untestable(PU): These are proven ATPG untestable and hard undetectable faults.
• ATPG_UNTESTABLE(AU): This fault class includes all the faults for which test generator unable to find the pattern to create a test. Testable faults become ATPG untestable faults because of constraints or limitations, placed on the ATPG tool such as pin constraint or an insufficient sequential depth. This faults may be detectable, if we remove some constraint, or change some limitations on the test generator
• UNDETECTED (UD): This fault class includes the undetected faults that cannot be proven untestable or atpg_untestable
  • uncontrolled(UC)
  • unobserved(UO)
    All the testable faults prior to ATPG are put in the UC category. Faults that remain UC or UO after APTG aborted, which means that with higher abort limit may reduce the UC and UO fault class

DFT:Ad-hoc methods, Structured methods,Scan cell

Design for Testability (DFT) is required to guarantee the product quality, reliability, performances, etc. Design for Testability refers to those design techniques that

• Enhances testability of device
• Ease ability to generate vectors
• Reduce test time
• Reduce the cost involved during test

There are different methods to implement the DFT Logic for Digital circuits which are listed below

• Ad-hoc methods: Good design practices learnt through experience and those methods are used as guidelines
  • Avoid combinational feedback
  • All flip flops must be initializable
  • Avoid redundant and large fanin gates
  • Provide test control for the signals which are not controllable
  • While designing test logic we have to consider the ATE requirements

Ad-hoc methods had few disadvantages, and these gives more advantage to Structured methods.

• Disdvantages od ad-hoc DFT methods:
  • Experts and tools not always available
  • Test generation is often manual with no guarantee of high fault coverage
  • Design iterations may be necessary

• Structured Methods: Structured DFT provides a more systematic and automatic approach to enhancing design testability. Structured DFT’s goal is to increase the controllability and observability of a circuit. Various methods exist for accomplishing this. The most common is the scan design technique, which modifies the internal sequential circuitry of the design.
  • Scan: In the design all the flip flops are converted to scan flip flop.
  • Boundary Scan
  • Built-in self-test

we have came across the scan flip flop, and you may be wondering, what would be the difference between a norml flip flop and a scan flip flop. Below pictorial representation give clear picture about a flop and scan flop.

TM represents Test Mode signal and this signal should be 1 during DFT testing and 0 for functional model.

Types of DFT Logic

Design for Testability circuit is used for controllability and observability of the design. The test logic is inserted in to the main core logic for testing the chip once it is manufactured. Types of DFT logic are

• Logic BIST
  Build in self-test is inserted into the core logic design. This circuit is used to test the core logic.

• MBIST
  Memory build in self-test is carried on the memory elements and this logic is used for testing memories

• Boundary Scan
  In the board level Boundary Scan circuitry provides the access to the inputs and output ports of the chips. This circuitry not only does board level testing, it can also do circuit level such as BIST or internal scan and it can test board interconnection. To control all these operation, TAP controller was used.

T3 Violation in DFT

Pattern are generated on the DFT logic inserted design, before generating the pattern the tool will check for certain rules and reports DRC violations as a part of ATPG flow. One of the rule is Tracing of scan chains from output pin to scan input pin, if the tool is unable to trace back, it will through a Trace (T rule) violation.

When the shift procedure failed to create a path from scan chain output pin back to scan chain input pin, then tool reports a trace violation (T-3). In this case engineer as to take care to properly constrain the input pins which are responsible for activating the DFT logic in the design. T3 violation can occur due to many reasons, few of them are explained below

Case I:

In this case as shown below after tracing till 10^th scan cell, chain tracing was blocked due the BLACK BOX present in the scan chain path and reports T3 violation by tool.

This can be solved by loading the BLACK BOX definition during the setup phase, which will help the tool to trace the chain from scan_out pin to scan_in pin  

Case II:

In this case shown below, there is a trace blockage in scan chain at 2^nd cell as there is no toggling activity of clock. When we trace back the clock pin, we can see that clock is coming from a mux and select line for mux is x.

This can be solved by making clock of FF3 to toggle, which makes the input D to appear at output pin of FF3. This makes the select line to low (i.e. is 0) and the D0 pin will be selected, which is toggling.

We have to make the clk1 pin to toggle, constraint the D pin of FF3 to 1 and we need to inform the tool about the constraints by following commands in a do file.
add_clock 0 clk1
add_input_constraint D –c0

We also need to modify the test procedure to pulse the clk1.
Template gen_tp =
offstate “clk1” 0 ;
force_pi 0 ;
 measure_po  100 ;
pulse clk1 200 100 ;
period 400 ;
end;

procedure test_setup =
temeplate gen_tp ;
cycle =
force D 0 ;
pulse clk1 ;
end ;
end;

Test coverage, Fault coverage

Test coverage and Fault coverage are the two important quantities which measures how good the DFT logic was implemented on core design for controllability and observability of a design.

Test Coverage:
Test coverage is a measure of test quality of DFT, is the percentage of faults detected from among all testable faults. This is the number of most concern when you consider the testability of the design

Fault Coverage:
Fault Coverage consists of the percentage of faults detected from among all the faults that the test patterns generated by the tool

Where DT is detected faults class includes all the faults that the ATPG identifies as detected and this are classified into two groups

• Det_simulation (DS)
• Det_implication (DI)

PD – posdet or possible detected fault class includes all the faults that fault simulation identifies as possible detected but not hard to detect
Let us see how the test coverage and fault coverage was calculated from snap shot of status report

                                                  report_statistics of faults

From the report Total no of faults are given as 302778
Faults due to unused pins (UU), Tied pins (TI), Blocked Pins (BL), and redundant logic (RE) are untestable by tool and this faults must be excluded from the total number of faults while calculating the Test Coverage and considered while calculating the Fault Coverage.

UU+TI+BL+RE => 4984+1076+12+1072 = 7144

Thus Testable faults are given asTotal Faults – (UU+TI+BL+RE)
Total faults detected during simulation (DS) and implication (DI) are

DS +DI => 202752+75601+16 = 278369

In general posdet_credit will be set to zero and with this above faults numbers we can have Test Coverage and Fault Coverage

  

In this process TC and FC are calculated and we need to achieve 99 % Test Coverage for Stuck At fault model and 95% Test Coverage for At Speed fault model

Design For Testability

DFT means Design for testability, where logic will be implemented or inserted in the core design at RTL stage(Now a days most of the company prefer at RTL stage) or Netlist stage. This test circuit verifies that core design does not have manufacturing defects focusing on circuit structure rather than functional behavior.

Manufacturing defects may include

• Short circuits
• Open interconnects
• Power and ground shorts

Manufacturing defects remain undetected by functional testing and these can cause undesirable behaviour during circuit operation. DFT helps to find the manufactured defects and improves the quality, yield of products.

Now you may wonder what is the use of Functional testing.Functional testing verifies your circuit performs .For example assume that your design is an Half adder circuit , Functional test verifies that circuit performs the addition operation and computes the correct results over the range of patterns