does knowlege on Location of MEMORIES was important during mbist implementation

MBIST( Memory Built In Self Test) is implemented to test memories in the design for different types of faults. MBIST contains the processor and wrapper which will be wrapped arround the memories.The MBIST processor controlls the wrapper and generates various control signals during the memory testing. A design may have multiple processors depending on the number of memories, memory size, power, frequency and memory placement.

Memories which are placed near by are grouped together and controlled by single processor. Thereofore, we need the memory placement info to group the memories under a controller and this info was given to the DFT team in the form of DEF and floorplan snapshot. This info will be given by PD/PNR team.

What happens if memories are not grouped properly?
If memories are not grouped properly according to their physical location i.e memories under same processors are sitting at different corners. This will lead to MBIST logic spreading, which impacts on MBIST timing during the STA due to long paths or increase in congestion due to lots of criss-cross while implementing the PNR and also increases the unneccesary power consumtption.

Types of DFT Logic

Design for Testability circuit is used for controllability and observability of the design. The test logic is inserted in to the main core logic for testing the chip once it is manufactured. Types of DFT logic are

• Logic BIST
  Build in self-test is inserted into the core logic design. This circuit is used to test the core logic.

• MBIST
  Memory build in self-test is carried on the memory elements and this logic is used for testing memories

• Boundary Scan
  In the board level Boundary Scan circuitry provides the access to the inputs and output ports of the chips. This circuitry not only does board level testing, it can also do circuit level such as BIST or internal scan and it can test board interconnection. To control all these operation, TAP controller was used.