Before implementing the logic, we will have a look at the truth table of the NAND gate and the inverter.
NAND GATE
A
B
O
0
0
1
0
1
1
1
0
1
1
1
0
NOT GATE
A
O
0
1
1
0
Fro the NAND gate truth table we can conclude the following When both the inputs are zero(0) ==> output is 1 (same as inverter) when both the inputs are one(1) ==> output is 0 (same as inverter)
Thus we can implement the not gate by connecting the both inputs together as shown below
There is another way of implementation of inverter using NAND gate , from truth table when input pin A is high (logic one) Nand gate behavious as INVERTER
Before implementing the logic, we will have a look at the truth table of the NOR gate and the inverter.
NOR GATE
A
B
O
0
0
1
0
1
0
1
0
0
1
1
0
NOT GATE
A
O
0
1
1
0
case I: From the NOR truth table we can see that when both the inputs are zero(0) ==> output is 1(same as inverter) both the inputs are one (1) ==> output is 0 (same as inverter)
Case II : second way of implementation of Inverter using Nor Gate.
NAND gates are preferred over NOR gates, because of below factors
Delay offered by NAND gate is less than NOR gate
Also NAND gate takes less size.
Low to high and high to low time are more symmentrical in NAND based design than in NOR based design
Before understanding why NAND gate offers less delay compare to NOR gate, we need to understand the pmos and nmos in circuit level and also different delays. RC equivalent circuit of nmos and pmos with width k is shown in fig 1.
Fig 1: NMOS and PMOS
Lets us analyse the rc model of inverter (with kn=1 and kp=2) which is connected to another inverter of same kn and kp value as shown in below fig 2.
Have you noticed width of pmos(kp) is twice the nmos(kn), what could be the reason?
In inverter nmos and pmos are connected in series and therefore current through the pmos must be equal to nmos. As mobility of holes are less and offers more resistance, thus to increase the flow of holes channel width of pmos is made twice that of nmos channel width. The elmore delay of the previous ciruit is show below and from this circuit we can calculate all the delays of circuit.
Fig 3: RC model of two inverters connected back to back
Delay of any device can expressed as sum of parasitic delay and effort delay/stage effort that depends on complexity and fan-out of the gate d=p+f p————–is the delay of the gate/device when no load is attached. f—————is the effort delay f=gh The complexity is represented by the logical effort, g and this defined as ratio of input capacitance of a gate to the input capacitance of an inverter that as same drive strength (i.e. delivers same current).
Electrical effort is denoted by h, If the load does not contain identical copies of the gate, the electrical effort can be computed as h = Cload / Cdriver Cload is the capacitance of the external load Cdriver is the driving capacitence of the gate
Now let us consider a two inputs NAND gate and NOR gate , both drives a same external load(Cout =4). Parasitic delay for inverter, NOR, NAND gates approximately equal to number of inputs. Therefore parasitic delay for 2 i/ps NAND and NOR gates are approximately equal to 2 and this delay increases as the no of inputs increase. Assume both NAND and NOR gate have same driving capacity( Cdriver =4) and drives same load capacity ( Cload =12) , then electricl effort(h) for both gates will be equal to 3.
The logical effort the gates are follows
Fig 4 : NAND Gate
Fig 5: Nor Gate
Delay offer by NOR gate is 7ns which is more than the delay offered by NAND gate.Thus the circuits design with NAND gate offers less delay compared with the ciruit design with NOR gate and therefore as a engineer we need to prefer NAND gate over NOR gate in circuit designing.
