Showing posts with label PLD. Show all posts
Showing posts with label PLD. Show all posts

Saturday 22 June 2024

Vlsi Design Styles in Digital Design

Digital Design can be implemented by various design styles. And depending on the market requirement different design styles are used.

  • Programmable Logic Design
    • Field Programmable Gate Array (FPGA)
    • Gate Array
  • Standard Cell (semi custom design)
  • Full Custom Design
  • Field Programmable Gate Array (FPGA):
    • Using VHDL or verilog
    • Implementation
      • Placement and Routing
      • BitStream Generation
      • Analyse timing, view layout, simulations etc
  • Gate Array: Gate Array design implementation is done with metal design and processing. The implementation requires two-step manufacturing process
    • First phase, which is based on standard masks, results in an array of uncommitted transistors on each GA chips
    • These uncommitted chips can be customized later, which is completed by defining the metal interconnects between the transistor of the array
    • In this chip utilization factor is higher than that of FPGA
    • Chip speed is higher
  • Standard Cell or Semi Custom Design:
    • The standard-cells based design is often called semi custom design.
    • The cells are pre-designed for general use and the same cells are utilized in many different chip designs. 
  • Full Custom Design
    • Full custom design involves creating IC where each individual transistors architecture and interconnections are specified. Designers manually place transistors, resistors,capacitors and other components at the transistor level

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