Perl_Series I

Assume the file contains 10 words and we need to find the longest word and print on the console with help of perl script. Following are different ways to open a file and read the content using perl

• less than < sign indicates that file has to be opend in read-only mode.
  open(DATA, “<vlsispace.txt”)
• greater than > sign indicates that file has to be opend in the writing mode.
  open(DATA, “>vlsispace.txt”)
• To open a file for updating without truncating it 
  open(DATA, “+<vlsispace.txt”)
• To truncate the file first 
  open DATA, “+>vlsispace.txt”
• In this mode, writing point will be set to the end of the file and append new data to file
  open(DATA,”>>vlsispace.txt”)
• To read the data in a file during append process
  open(DATA,”+>>vlsispace.txt”)

#!usr/bin/perl
open r,”<data.txt” or “cannot open the file”;
@string_words;
while($a=<r>)
{
chomp($a);
$i++;
@string_words[$i]=$a;
}
foreach $d(@string_words)
{
$i=length($d);
if($max<$i)
{
$word=$d;
$max=$i;
}
}
print “@string_words\n”;
print “the longest word:$word\n”;
print “the length of the longest word:$max\n”;
close r;

False Paths:set_false_path

During the timing analysis, tools verifies whether logic paths meets all the constraints defined in the SDC (Synopsys design constraints) and reports violation if any logic paths doesn’t meet the required timings. And the tools are not intelligent enough to find which logic path was true or false path. Therefore, we must inform the tool which are the false paths before performing the timing analysis. Few cases are mentioned below.
Case I

During the Functional mode the select line of mux is tied to 0 and tool should not perform the timing analysis on this path (marked in orange) which will be active during DFT test mode. This information must be provided to the following command
set_flase_path -to <list of end points>

Case II:
We need to add false path on the pins which are tied to low or high (static signals). As they are static signals, timing checks are not necessary.
set_false_path -from [get_ports A]

Case III:
If two clocks are not related to each other (Asynchronous) then we must define these paths as false path. In this case to avoid any setup/hold violations at capturing registers some synchronizers technique must be employed. Few of the techniques are

• Two flop Synchronizers
•  FIFO
•  Handshaking protocol

set_false_path -from CLKA   -to CLKB

In case of the two flip flop synchronizers as show in above figure timing checks are not necessary between the Launching flop and the 1^st stage of the synchronizers. Therefore, we have to consider the signal to Flop FF2 as false path