A Vec in chisel represents a collections signal (same type). These are similar to the array data structures in other languages. Each element in Vec can be accessed by an index. A Vec will be created by calling a constructor with two parameters:
- The number of elements
- The type of the elements
The combinations vec must be wrap into a wire.
val vs = Wire(Vec(3 , UInt(4.W)))
Individual elements of the vecot can be accessed by index
vs(0) := 1.U
vs(1) := 2.U
vs(2) := 3.U
A vector wrapped into a Wire is multiplexer. We can also wrap the vec into register to define the array of registers as shown below
val regfile = Reg(Vec(32, UInt(32.W))
The elements of that register are accessed by index
val idx = 1.U(2.W)
val dout = regfile(idx)
We can freely mix bundles and vectors, as shown below
val vecBundle = Wire(Vec(8, new vlsiscape() ) ) —> vlsispace() was a bundle defined
