CHISEL : Vec

A Vec in chisel represents a collections signal (same type). These are similar to the array data structures in other languages. Each element in Vec can be accessed by an index. A Vec will be created by calling a constructor with two parameters:

• The number of elements
• The type of the elements

The combinations vec must be wrap into a wire.
val vs = Wire(Vec(3 , UInt(4.W)))

Individual elements of the vecot can be accessed by index
vs(0) := 1.U
vs(1) := 2.U
vs(2) := 3.U

A vector wrapped into a Wire is multiplexer. We can also wrap the vec into register to define the array of registers as shown below
val regfile = Reg(Vec(32, UInt(32.W))
The elements of that register are accessed by index
val idx = 1.U(2.W)
val dout = regfile(idx)

We can freely mix bundles and vectors, as shown below

val vecBundle = Wire(Vec(8, new vlsiscape() ) ) —> vlsispace() was a bundle defined

CHISEL : Bundle

In Chisel provides two constructs to group related signals

• A Bundle to group signals of different type.
• A Vec represents the collection of signal of same type.

A chisel Bundle groups several signals. The entire bundle can be accessed or individual field can be accessed by their names. User or Designer can define a bundle(collections of signals) by definnig a class which extends Bundle and list the fields as vals within the constructor block

class vlsispace() extends Bundle {
val vlsi = UInt(32.W)
val space = Bool()
}

To access the bundle in following way
val vs = Wire(new vlsispace())
vs.vlsi := 124.U
vs.space := false.B

val a = vs.space

By using the dot we can access the field of the particular constructor, which is commonly used in object oriented programming. A Bundle is similar to struct in C , a record in VHDL or struct in system verilog. A bundle can be referred as a whole as follows

val channel = vs

A bundle may as well contain a vector:

class BundleVec extends Bundle {
val vs = UInt(8.U)
val vector = Vec(4 , UInt(4,W))
}

When we want a register of a bundle type that needs a reset value, we first wire of that bundle and define the values for the bundle elements and then passing the bundle to RegInit:

val initval = Wire( new vlsispcae())
initval.vlsi := 1.U
initval.space := true.B

val channelreg = RegInt(initval)

CHISEL: Counter in Chisel

In digital systems counter is plays a main role. Counters are used to keep a track of events , time intervals and no of interrupts etc. . Counter can be programmed in many languages like verilog, c , c++ , java, python, chisel etc. In this post we will see how to program a counter in chisel language.

Design a counter which starts counting from 0 till 9 and reset to 0 once it counts till 9.

val cntSpace = RegInit (0.U (8.U))—> defines a 8 bit register which initialize to 0 upon reset signal
cntSpace := Mux( cntSpace ===9.U , 0.U, cntSpace + 1.U)

:= ——> update register
When the cntSpace reaches to 9, it will initialize to 0 otherwise the cntSpace will be incremented by one

chisel:Registers

In digital design, register are the basic elements which are used widely. Chisel provides a register , which is collection of D Flip Flops. The register is connected to a clock and the output of the register updates on every rising edge. When an initialization value is provided at the declaration of thr register, it uses a synchronous reset connected to reset signal. A register can be any chisel type that can be represented as a collection of bits.

Below line defines an 8 bit register, initialized with 0 at reset:
val reg = RegInit(0.U(8.W))

An input is connected to the register with the := update operator and the output of the register can be used just with the name in an expression

reg := d
val q = reg

A register can also be connected to its input at the definition:

val nextReg = RegNext(d)

A register can also be initialized during the definition:

val bothReg = RegNext(d, 0.U)

CHISEL:multiplexer

A multiplexer is a circuit which selects between the input signals depending on select signal. In basic form of multipexer (2:1 mux) selects between two signals. Below fig represents the 2:1 multiplexer , depending upon the sel signal y will represent the input signal a or b

A multiplexer can be designed using logic gates. As the multiplexer is used more frequently in digital desgin, chisel provides the function called MUX

val results = Mux(sel , a, b)

where a is selected when sel is true, otherwise b is selected, type of sel is a chisel Bool. The inputs a and b can be any chisel base type or aggregate (bundlers or vectors) as long as they are same type

A Bundle to group signals of different types. A Vec to represents an indexable collection of signals of the same type

CHISEL:Combinational circuits

Chisel uses the boolean algebra operators and arithmetic operators same as in c, java, scala, etc programming languages.

val sel = a & b

The keyword val is part of scala which is used to name the variables that have values that won’t change. And here it is used to name the chisel wire, sel, holding the output of the bitwise and operation. A signal can also first be defined as a Wire of some type. Afterward, we can assign a value to the wire with the  ‘:=’ update operator.

val sel = Wire(UInt()))
sel := a & b

Boolean operators

& —– represents bitwise AND operator
val and = a & b
| —– represents bitwise OR operator
val or = a | b
^ —– represents bitwise XOR operator
val xor = a ^ b
~ —– represents bitwise negation
val not = ~a

Arithmetic operations

+ —– Addition operation
val add = a + b
– —– Subtraction operation
val sub = a – b
* —– multiplication operation
val mul = a * b
/ —– division operation
val div = a / b
% —– modulo operation
val mod = a % b

Operator	Description	Data Types
*        /         %	Multiplication, division, modulus	UInt, SInt
+       –	Addition, subtraction	UInt, SInt
===      =/=	Equal, not equal	UInt, SInt, returns Bool
>    >=    <=	Comparison operations	UInt, SInt, returns Bool
<<      >>	Shift left, shift right	UInt, SInt
~	NOT	UInt, SInt, Bool
&        |        ^	AND, OR, XOR	UInt, SInt, Bool
!	Logical NOT	Bool
&&      ||	Logical AND, OR	Bool

Chisel defined hardware operators are show above

CHISEL:DATA TYPES

Chisel data types are used to specify the type of values held in the state elements or flowing on wires. Chisel defines the Bundles for making collection of values with named fields (Similar to Structs in other languages and Vecs for indexable collections of values. There are three data types (which represents the vector of bits) to describe the signals, combinational logic, registers.

• Bits
• UInt (Unsigned Integer)
• SInt (Signed Integer)

UInt and SInt extends the Bits data type. The Chisel uses the two’s complement as signed integer representation. Definition for three data types as follows

Bits (8.W)  –> an 8 bit width Bits
UInt (8.W) –> an 8 bit width unsigned Integer
SInt (8.W) –> an 8 bit width Signed Integer

Example:

0.U    //defines the Unsigned Integer constant of 0
-3.S // defines the Signed Integer constant of -3

We can also define the Integer with width.

7.U(4.W)  // defines the Unsigned Integer of width 4
8.S(7.W) // Signed decimal 7 bit literal of type SInt

For constants defined in other bases than decimal, the constant is defined in a string with a preceding h for hexdecimal(base 16), o for octal(base 8), b for binary (base 2). In these case we omit the bit width and the chisel infers the minimum width to fit the constants in, in this below case width 8 will be considered.

“hdf”.U    // Hexa decimal representation of 223
“o337”.U  // Octal representation of 223
“b1101_1111”.U  // Binary representation of 223

CHISEL

Chisel (Constructing Hardware in a Scala Embedded Language)

Is a new hardware language which made open source by UC Berkeley. Chisel supports the advance hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel provides the flexibility of concepts like object orientation, functional programming, parameterized types and type inference over the VHDL or Verilog hardware languages. Chisel adds hardware construction primitives to the scala programming language, providing designers with power of a modern programming language to write complex, prameterizable circuit generators that produce sythesizble Verilog. With single chisel code, we can generate a high-speed C++ based cycle –accurate software simulator, or low-level Verilog design for ASIC or FPGA for synthesis, place and route.

Chisel is powered by FIRRTL (highly parameterized generators and layered domain-specific hardware languages), a hardware complier that performs optimization of chisel-generated circuits.
Steps involved to generate the Verilog from chisel code

1. The Chisel stage/Font-end compiles chisel to a circuit intermediate representation called FIRRTL(highly parameterized generators and layered domain-specific hardware languages
2. FIRRTL stage/ mid-end then optimizes FIRRTL and then applies user custom transformations
3. Finally the Verilog stage/Backend generated the Verilog based on the optimized FIRRTL.