Any digital design should be free from setup and hold violation. First, we will understand what is Setup and Hold time. Below fig is simple circuit with launch and capture flipflop, these are ideal flip flop (means setup time and hold time are zero)
Setup time is the minimum amount of time a synchronous data input should be held steady before the clock event so that the data input is reliably sampled by the clock event.
Hold time is the minimum amount of time a synchronous data input should be held steady after the clock event so that the data input is reliably sampled by the clock event.
Any design to work perfectly setup and hold slack must be positive. What is slack?
Slack is defined as difference between required arrival time to actual arrival time of the signal. There are setup and hold slack. Design works well if both the slacks are positive and there will be violation if any of them or both are -ve
Setup Slack is the difference between the Required time and Arrival time of the signal at capture flip flop. During the setup calculation we must take max delay values in data path and min values in clock path and the setup slack must be greater than zero for violation free circuit. Setup check is carried at next clock edge.
Setup slack=RT-AT
RT——-required time
AT——-arrival time
RT= clock_period(tp)+clock_network_delay(tc)-setup_time(tsu)
AT=flip_flop_delay(tc2q) +wire_delay(tw)+comb_delay(td)
Hold Slack is the difference between the Arrival time and the required time of the data signal. During the Hold calculation we must take min delay values in data path and max values in clock path and the hold slack must be greater than zero for violation free circuit. Hold check is done on same clock edge
Hold Slack =AT-RT
RT= clock_period(tp)+clock_network_delay(tc)+hold_time(th)
AT=flip_flop_delay(tc2q) +wire_delay(tw)+comb_delay(td)
Note: As hold analysis is carried on same clock, we must make clock_period to zero(tp=0)
How to we overcome the setup or hold violation
Setup violation occurs when the data arrives late at the capture flip flop and this can be avoided by reducing the delay in the data path. Delay in data path can be reduced in different steps
- LVT cells offers less delay, we can swap the HVT cells to LVT cells
- High drive strength cells delay is less compared to low drive strength and we can swap between the low drive strength cell to high drive strength cell, but we need compromise with the power.
- If we can comprise with speed of the design, then clock frequency can be reduced to avoid the setup violation.
Hold violation occurs when the data arrives early at the capture flip flop and we need add delays in the data path to avoid the hold violation. We can do any of the steps to increase the delay in the data path
- We need to add the buffers in the data path
- Swap HVT cells to LVT cells
- Swap high drive strength cells to low drive strength cells
