Showing posts with label scan cells. Show all posts
Showing posts with label scan cells. Show all posts

Wednesday, 15 July 2020

scan cell, scan chain

Scan cell is one of the DFT technique , to test the sequential circuits in the Asic/Soc design. Normal D flip flop are converted to scan flip flop, if the tool meets the following criteria

  • Clock of the flip flop must be controllable
  • The set/reset of the flops must be inactive during the shift mode.


Once the all the flops in the design meet the above two rules the tool will convert the d flops to scan flops by adding a mux as shown in figure above. Then the tools will stitch the scan cells into a scan chain according to the design requirements.


When Scan Enable is 0 (SE=0), all the scan chains in the design will be disconnected and the flops are connected to comb. logic


When Scan Enable is 1 (SE=1) , combinational logic will be bypassed and all scan cells will be connected to form a scan chain


When SE=1 , patterns are loaded to the scan chains and the data from the comb logic are captured when SE=0

Physical Cells :TAP CELLS, TIE CELLS, ENDCAP CELLS, DECAP CELLS

Tap Cells (Well Taps) :  These library cells connect the power and ground connections to the substrate and n­wells, respectively.  By plac...