SDC (Synopsys design Constraints)

SDC abbrevates to Synopsys design constraints which has information of timing, area and power constraints for the design and this files are in TCL format. The front end( rtl designer) adds the required constraints to the design and then dft team adds the required constraints to sdc file. In few companies STA engineer will responsible for creating the SDC file. Below are the list of commands with which SDC files are created.

• Operating conditions
  • set_operating_condition
    Sets the required operating conditions for the timing analysis. Type of analysis can be single, wc_bc or on chip variation. We can find the operating condition in the libraries that are defined using operating_conditions command Operating conditions
• System Interface
  • set_drive
    It specifies the drive strength of the input port and external drive resistance of the port
  • set_driving_cell
    Is used to model the drive resistance of the cell driving the input port
  • set_fanout_load
    specifies the fanout load on the output port of the cells
  • set_input_transition
    sets the transition time on the input port with respect to the clock defined
    ex: set_input_transition 0.4 [get_ports pin_name]
  • set_load
    set the value of capacitive load on the output port or net
• Design rule constraints
  • set_max_capacitance
    specifies the max capacitance on all the ports in the design
  • set_max_fanout
    specifies the max fanout for all the ports or on a design
  • set_max_transition
    specifies the max transition value for the port or on a design
  • set_min_capacitance
    specifies the min capacitance value for the port or on the design
  • set_resistance
    Specifies the resistance value for the given nets