Showing posts with label standard Cells. Show all posts
Showing posts with label standard Cells. Show all posts

Saturday 22 June 2024

STANDARD CELLS IN DIGITAL DESIGN/VLSI

Standard cell are well defined cells which are used in Digital Design more frequently. To name few AND, NOR, NAND, XOR ,etc belongs to standard cell family. All the standard cells from one library will have equal drive strength  and  equal height. Standard cell Architecture is defined based on  cell height which is determined on the basis of the number of trackes , beta ratio, pitch and transistor widths. To attain the similarity amoung the cells and aboid the alignment issues ,standard cells are designed with fixed height

The height of a standard cell can be calculated by considering number of tracks required for power rail, ground rail, I/O pins and routing. Often the standard cells are available in single height and double height. The Double height cells are the high density cells and are used for ultra high speed operations 

STANDARD CELL DESIGN METHODOLOGY

  • VDD and GND should be of same height and parallel. Both the power rails used metal M1
  • make sure within the cell all the PMOS should occupy top and all NMOS should occupy bottom of the Layout
  • Preferred Practice:  Diffusion layer for all the transistor in a row
  • All the gates include the gate and substrate


 Layout for any schematic can be drawn in many ways. Layout of INVERTER can be drawn in two different ways.


In the Fig 2 was preferred layout as all the PMOS will be in one level and all the NOMS will be at one level, and also the poly gates are drawn vertical and these are common to nmos and pmos transistors. 

One more layout example with NAND GATE


There are many reasons for choosing the FIG 2 and FIG 3 as most preferred Layout
  • Save the Design Area: Both the nwell and pwell are in the same level for all the standard cell, so make a common well which saves lots of areas 
  • Easy Placement for APR tool: All the standard cells have the same height and easily can be fit into the standard cell row so make it easy for APR (Automatic Place and Route) to place them. They also have power rails in the same location for all the standard cells, so power rails can also be abutted easily 
  • Easy to Route: All the pins of standard cells are in the intersection of horizontal and vertical tracks, So it becomes easy to route them by the APR tool . 

What is Verilog

  What is Verilog? Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designe...