STANDARD CELLS IN DIGITAL DESIGN/VLSI

Standard cell are well defined cells which are used in Digital Design more frequently. To name few AND, NOR, NAND, XOR ,etc belongs to standard cell family. All the standard cells from one library will have equal drive strength  and  equal height. Standard cell Architecture is defined based on  cell height which is determined on the basis of the number of trackes , beta ratio, pitch and transistor widths. To attain the similarity amoung the cells and aboid the alignment issues ,standard cells are designed with fixed height

The height of a standard cell can be calculated by considering number of tracks required for power rail, ground rail, I/O pins and routing. Often the standard cells are available in single height and double height. The Double height cells are the high density cells and are used for ultra high speed operations 

STANDARD CELL DESIGN METHODOLOGY

• VDD and GND should be of same height and parallel. Both the power rails used metal M1
• make sure within the cell all the PMOS should occupy top and all NMOS should occupy bottom of the Layout
• Preferred Practice:  Diffusion layer for all the transistor in a row
• All the gates include the gate and substrate

 Layout for any schematic can be drawn in many ways. Layout of INVERTER can be drawn in two different ways.

In the Fig 2 was preferred layout as all the PMOS will be in one level and all the NOMS will be at one level, and also the poly gates are drawn vertical and these are common to nmos and pmos transistors. 

One more layout example with NAND GATE

There are many reasons for choosing the FIG 2 and FIG 3 as most preferred Layout

• Save the Design Area: Both the nwell and pwell are in the same level for all the standard cell, so make a common well which saves lots of areas 
• Easy Placement for APR tool: All the standard cells have the same height and easily can be fit into the standard cell row so make it easy for APR (Automatic Place and Route) to place them. They also have power rails in the same location for all the standard cells, so power rails can also be abutted easily 
• Easy to Route: All the pins of standard cells are in the intersection of horizontal and vertical tracks, So it becomes easy to route them by the APR tool . 

Different Cells in Digital Design

 In any digital design apart from the standard cell , we need to different Physical Cell to minimize the issues in the design. 

• Standard Cells
• Tap Cells
• End cap Cells
• ICG Cells
• DECAP Cells
• Filler Cells
• ESD Clamps
• Tie Cells
• Spare Cells
• Delay Cells
• Metrology Cells

CROSS TALK

Crosstalk noise: noise refers to undesired or unintentional effect between two or more signals that are going to affect the proper functionality of the chip. It is caused by capacitive coupling between neighboring signals on the die. In deep submicron technologies, noise plays an important role in terms of functionality or timing of device due to several reasons.

• Increasing the number of metal layers. For example, 28nm has 7 or 8 metal layers and in 7nm it’s around 15 metal layers.
• Vertically dominant metal aspect ratio it means that in lower technology wire are thin and tall but in higher technology the wire is wide and thin, thus a greater the proportion of the sidewall capacitance which maps into wire to wire capacitance between neighboring wires.
• Higher routing density due to finer geometry means more metal layers are packed in close physical proximity.
• A large number of interacting devices and interconnect.
• Faster waveforms due to higher frequencies. Fast edge rates cause more current spikes as well as greater coupling impact on the neighboring cells.
• Lower supply voltage, because the supply voltage is reduced it leaves a small margin for noise.
• The switching activity on one net can affect on the coupled signal. The effected signal is called the victim and affecting signals termed as aggressors.

There are two types of noise effect caused by crosstalk

• Glitch: when one net is switching and another net is constant then switching signal may cause spikes on the other net because of coupling capacitance (Cc) occur between two nets this is called crosstalk noise.

In fig the positive glitch is induced by crosstalk from rising edge waveform at the aggressor net. The magnitude of glitch depends on various factors.

• Coupling capacitance between aggressor and victim net: greater the coupling capacitance, larger the magnitude of glitch.
• Slew (transition) of the aggressor net: if the transition is more so magnitude of glitch also more. And we know the transition is more because of high output drive strength.
• If Victim net grounded capacitance is small then the magnitude of glitch will be large.
• If Victim net drive strength is small then the magnitude of glitch will be large.

Types of glitches:

• Rise: when a victim net is low (constant 0) and the aggressor net is at a rising edge.

• Fall: when a victim net is high (constant 1) and the aggressor net is at the falling edge.

• Overshoot: when a victim net is high (constant 1)) and the aggressor net is at a rising edge.

• Undershoot: when a victim net is low (constant 0) and the aggressor net is at the falling edge.

Crosstalk delay: 

when both nets are switching or in transition state then switching signal at the victim signal may have some delay or advancement in the transition due to coupling capacitance (Cc) occur between two nets this is called crosstalk delay.
Crosstalk delay depends on the switching direction of aggressor and victim net because of this either transition is slower or faster of the victim net.


Types of crosstalk:
Positive crosstalk: the aggressor net has a rising transition at the same time when the victim net has a falling transition. The aggressor net switching in the opposite direction increases the delay for the victim. The positive crosstalk impacts the driving cell, as well as the net, interconnect - the delay for both gets increased because the charge required for the coupling capacitance Cc is more.

Negative crosstalk: the aggressor net is a rising transition at the same time as the victim net. The aggressor's net switching in the same direction decrease delay of the victim. The positive crosstalk impacts the driving cell, as well as the net, interconnect - the delay for both gets decreased because the charge required for the coupling capacitance Cc is less.

Crosstalk effect on timing analysis:

Consider crosstalk in data path:
If the aggressor transition in the same direction as the victim then victim transition becomes fast because of this data will be arrive early means arrival time will be less.
Setup = RT – AT(dec) this is good for setup #dec- decrease
Hold = AT(dec) – RT this is bad for hold

If the aggressor transition in a different direction as a victim then victim transition becomes slow because of this data will be arrive late means arrival time will be more.


Setup = RT – AT(inc) this is not good for setup
Hold = AT(inc) – RT this is good for hold #inc- increase

Consider crosstalk in the clock path:
If the aggressor transition in the same direction as the victim then victim transition becomes fast because of this clock will be arrive early means Required time will be less.

Setup = RT(dec) – AT this is not good for setup

Hold = AT – RT(dec) this is good for hold

If the aggressor transition in a different direction as a victim then victim transition becomes slow because of this clock will be arrive late means the Required time will be more.

Setup = RT(inc) – AT this is good for setup

Hold = AT – RT(inc) this is not good for hold

How to reduce the crosstalk:

• Wire spacing (NDR rules) by doing this we can reduce the coupling capacitance between two nets.
• Increased the drive strength of victim net and decrease the drive strength of aggressor net
• Jumping to higher layers (because higher layers have width is more)
• Insert buffer to split long nets
• Use multiple vias means less resistance then less RC delay
• Shielding: high-frequency noise is coupled to VSS or VDD since shielded layers are connects to either VDD or VSS. The coupling capacitance remains constant with VDD or VSS.

Data flow modeling

Dataflow modeling is a higher level of abstraction. The designer no need have any knowledge of logic circuit. He should be aware of data flow of the design. The gate level modeling becomes very complex for a VLSI circuit. Hence dataflow modeling became a very important way of implementing the design.
In dataflow modeling most of the design is implemented using continuous assignments, which are used to drive a value onto a net. The continuous assignments are made using the keyword assign.

The assign statement

The assign statement is used to make continuous assignment in the dataflow modeling. The assign statement usage is given below:

assign out = vs0 + vs1; // vs0 + vs1 is evaluated and then assigned to out.

• The LHS of assign statement must always be a scalar or vector net or a concatenation. It cannot be a register.
• Continuous statements are always active statements.
• Registers or nets or function calls can come in the RHS of the assignment.
• The RHS expression is evaluated whenever one of its operands changes. Then the result is assigned to the LHS.
• Delays can be specified.

Examples:

assign vs[3:0] = vs0[3:0] & vs1[3:0];

assign {o3, o2, o1, o0} = vs0[3:0] | {vs1[2:0],vs2}; // Use of concatenation.

Implicit Net Declaration:

wire vs0, vs1;
assign out = vs0 ^ vs1;

In the above example out is undeclared, but verilog makes an implicit net declaration for out.

Implicit Continuous Assignment:

wire out = vs0 ^ vs1;

The above line is the implicit continuous assignment. It is same as,

wire out;
assign out = in0 ^ in1;

Delays

There are three types of delays associated with dataflow modeling. They are: Normal/regular assignment delay, implicit continuous assignment delay and net declaration delay.

Normal/regular assignment delay:

assign #10 out = in0 | in1;

If there is any change in the operands in the RHS, then RHS expression will be evaluated after 10 units of time. Lets say that at time t, if there is change in one of the operands in the above example, then the expression is calculated at t+10 units of time. The value of RHS operands present at time t+10 is used to evaluate the expression.

Implicit continuous assignment delay:

wire #10 out = vs0 ^ vs1;

is same as

wire out;
assign 10 out = vs0 ^ vs1;

Net declaration delay:

wire #10 out;
assign out = vs;

is same as

wire out;
assign #10 out = vs;

Gate level Modelling

The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design

Gate primitives are predefined in Verilog, which are ready to use. They are instantiated like modules. There are two classes of gate primitives: Multiple input gate primitives and Single input gate primitives.
Multiple input gate primitives include and, nand, or, nor, xor, and xnor. These can have multiple inputs and a single output. They are instantiated as follows:

// Two input AND gate.
and and_1 (out, in0, in1);

// Three input AND gate.
and and_2 (out, in0, in1, in2);

// Two input OR gate.
or or_1 (out, in0, in1);

// Four input NOR gate.
or or_2 (out, in0, in1, in2, in3);

// Five input XOR gate.
xor xor_1 (out, in0, in1, in2, in3, in4);

// Two input XNOR gate.
xnor and_1 (out, in0, in1);

Single input gate primitives include not, buf, notif1, bufif1, notif0, and bufif0. These have a single input and one or more outputs. Gate primitives notif1, bufif1, notif0, and bufif0 have a control signal. The gates propagate if only control signal is asserted, else the output will be high impedance state (z). They are instantiated as follows:

// Inverting gate.
not not_1 (out, in);

// Two output buffer gate.
buf buf_1 (out0, out1, in);

// Single output Inverting gate with active-high control signal.
notif1 notif1_1 (out, in, ctrl);

// Double output buffer gate with active-high control signal.
bufif1 bufif1_1 (out0, out1, in, ctrl);

// Single output Inverting gate with active-low control signal.
notif0 notif0_1 (out, in, ctrl);

// Single output buffer gate with active-low control signal.
bufif0 bufif1_0 (out, in, ctrl);

Gate delays

Gate Delays

In Verilog, a designer can specify the gate delays in verilog code. This helps the designer to get a real time behavior of the logic circuit.

Rise delay: It is equal to the time taken by a gate output transition to 1, from another value 0, x, or z.

Fall delay: It is equal to the time taken by a gate output transition to 0, from another value 1, x, or z.

Turn-off delay: It is equal to the time taken by a gate output transition to high impedance state, from another value 1, x, or z.

• If the gate output changes to x, the minimum of the three delays is considered.
• If only one delay is specified, it is used for all delays.
• If two values are specified, they are considered as rise, and fall delays.
• If three values are specified, they are considered as rise, fall, and turn-off delays.
• The default value of all delays is zero.

and #(5) and_1 (out, in0, in1);
// All delay values are 5 time units.

and #(3,4,5) nand_1 (out, in0, in1);
// rise delay = 3, fall delay = 4, and turn-off delay = 5.

and #(3,4) or_1 (out, in0, in1);
// rise delay = 3, fall delay = 4, and turn-off delay = min(3,4) = 3.

There is another way of specifying delay times in verilog. Min:Typ:Max values for each delay. This helps designer to have a much better real time experience of design simulation, as in real time logic circuits the delays are not constant. The user can choose one of the delay values using +maxdelays, +typdelays, and +mindelays at run time. The typical value is the default value.

and #(4:5:6) and_1 (out, in0, in1);
// For all delay values: Min=4, Typ=5, Max=6.

and #(3:4:5,4:5:6,5:6:7) nand_1 (out, in0, in1);
// rise delay: Min=3, Typ=4, Max=5, fall delay: Min=4, Typ=5, Max=6, turn-off delay: Min=5, Typ=6, Max=7.

In the above example, if the designer chooses typical values, then rise delay = 4, fall delay = 5, turn-off delay = 6.

Basics : Data Types III

Vectors

Vectors can be a net or reg data types. They are declared as [high:low] or [low:high], but the left number is always the MSB of the vector.

wire [7:0] vs; // vs[7] is the MSB.
reg [0:15] vs_1; // vs_1[15] is the MSB.

In the above examples: If it is written as vs[5:2], it is the part of the entire vector which contains 4 bits in order: vs[5], vs[4], vs[3], vs[2].

Similarly vs_1[0:7], means the first half part of the vecotr vs_.1
Vector parts can also be specified in a different way:
vector_name[start_bit+:width] : part-select increments from start_bit in above example: vs_1[0:7] is same as vs_1[0+:8].

vector_name[start_bit-:width] : part-select decrements from start_bit in above example: vs[5:2] is same as vs[5-:4].

Arrays

Arrays of reg, integer, real, time, and vectors are allowed. Arrays are declared as follows:

reg vs1[0:7];
real vs3[15:0];
wire [0:3] vs4[7:0]; // Array of vector
integer vs5[0:3][6:0]; // Double dimensional array

Strings

Strings are register data types. For storing a character, we need a 8-bit register data type. So if you want to create string variable of length n. The string should be declared as register data type of length n*8.

reg [8*8-1:0] vs_1; // vs_1 is a string of length 8.

Time Data Types

Time data type is declared using the keyword time. These are generally used to store simulation time. In general it is 64-bit long.

time vs_1;
Vs_1 = $time; // assigns current simulation time to vs_1.

Basics : Data types II

Integers

Integer is a register data type of 32 bits. The only difference of declaring it as integer is that, it becomes a signed value. When you declare it as a 32 bit register (array) it is an unsigned value. It is declared using the keyword integer.

Real Number

Real number can be declared using the keyword real. They can be assigned values as follows:
real VS;

VS = 1.234; // Decimal notation.
VS = 3e4; // Scientific notation.

Parameter

Parameters are the constants that can be declared using the keyword parameter. Parameters are in general used for customization of a design. Parameters are declared as follows:

parameter vs = 123; // vs is a constant with value 123.

Keyword defparam can be used to change a parameter value at module instantiation. Keyword localparam is usedd to declare local parameters, this is used when their value should not be changed.

Synchronous Reset and Asynchronous Reset

A Reset is required to initialize a hardware design for system operation and to force an value into a known state for simulation.

A reset simply changes the state of the device to a user defined state. There are two types of reset, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active/negative edge of the clock.

Advantages:

• The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.
• Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.
• Synchronous resets provide some filtering for the reset signal such that it is not effected by glitches, unless they occur right at the clock edge. A synchronous reset is recommended for some types of designs where the reset is generated by a set of internal conditions. As the clock will filter the logic equation glitches between clock edges.

Disadvantages:

• The problem in this topology is with reset assertion. If the reset signal is not long enough to be captured at active clock edge (or the clock may be slow to capture the reset signal), it will result in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset pulse is wide enough to be present during the active clock edge.
• Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the reset signal from any other data signal. So proper care has to be taken with logic synthesis, else the reset signal may take the fastest path to the flip-flop input there by making worst case timing hard to meet.
• In some power saving designs the clocked is gated. In such designed only asynchronous reset will work.
• Faster designs that are demanding low data path timing, can not afford to have extra gates and additional net delays in the data path due to logic inserted to handle synchronous resets.

Asynchronous Reset

An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the clock signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.

Advantages:

• High speeds can be achieved, as the data path is independent of reset signal.
• Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.
• As in synchronous reset, no work around is required for logic synthesis.

Disadvantages:

• The problem with this type of reset occurs at logic de-assertion rather than at assertion like in synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.
• Spurious resets can happen due to reset signal glitches.

CHISEL : Vec

A Vec in chisel represents a collections signal (same type). These are similar to the array data structures in other languages. Each element in Vec can be accessed by an index. A Vec will be created by calling a constructor with two parameters:

• The number of elements
• The type of the elements

The combinations vec must be wrap into a wire.
val vs = Wire(Vec(3 , UInt(4.W)))

Individual elements of the vecot can be accessed by index
vs(0) := 1.U
vs(1) := 2.U
vs(2) := 3.U

A vector wrapped into a Wire is multiplexer. We can also wrap the vec into register to define the array of registers as shown below
val regfile = Reg(Vec(32, UInt(32.W))
The elements of that register are accessed by index
val idx = 1.U(2.W)
val dout = regfile(idx)

We can freely mix bundles and vectors, as shown below

val vecBundle = Wire(Vec(8, new vlsiscape() ) ) —> vlsispace() was a bundle defined

CHISEL : Bundle

In Chisel provides two constructs to group related signals

• A Bundle to group signals of different type.
• A Vec represents the collection of signal of same type.

A chisel Bundle groups several signals. The entire bundle can be accessed or individual field can be accessed by their names. User or Designer can define a bundle(collections of signals) by definnig a class which extends Bundle and list the fields as vals within the constructor block

class vlsispace() extends Bundle {
val vlsi = UInt(32.W)
val space = Bool()
}

To access the bundle in following way
val vs = Wire(new vlsispace())
vs.vlsi := 124.U
vs.space := false.B

val a = vs.space

By using the dot we can access the field of the particular constructor, which is commonly used in object oriented programming. A Bundle is similar to struct in C , a record in VHDL or struct in system verilog. A bundle can be referred as a whole as follows

val channel = vs

A bundle may as well contain a vector:

class BundleVec extends Bundle {
val vs = UInt(8.U)
val vector = Vec(4 , UInt(4,W))
}

When we want a register of a bundle type that needs a reset value, we first wire of that bundle and define the values for the bundle elements and then passing the bundle to RegInit:

val initval = Wire( new vlsispcae())
initval.vlsi := 1.U
initval.space := true.B

val channelreg = RegInt(initval)

n bit binary adder or ripple carry adder

By using full adder, a single 1-bit binary adders can be constructed from basic logic gates as shown below

But what if we wanted to add together two n-bit numbers, then n number of 1-bit full adders need to be connected or “cascaded” together to produce a adder known as a Ripple Carry Adder.

Ripple carry adder is simply “n“ number of 1-bit full adders cascaded together with full adder representing a single weighted column in a long binary addition. It is called a ripple carry adder because the carry signals produce a “ripple” effect through the binary adder from LSB to MSB.

Let us consider a three bit full adders to “add” together two 3-bit numbers, the two outputs of the first full adder will provide the first place digit sum (S) of the addition plus a carry-out bit that acts as the carry-in digit of the next binary adder. The second binary adder in the chain also produces a summed output (the 2nd bit) plus another carry-out bit and we can keep adding more full adders to the combination to add larger numbers, linking the carry bit output from the first full binary adder to the next full adder, and so forth. An example of a 3-bit adder is given below.

Let us consider A =4 , B=3, sum of A and B will be 7. In binary addition

There will be a overflow ,If the sum was greater than or equal to 2ⁿ one of the disadvantage in this adder. Let us consider A =4 , B=4, Sum of A and B will be 8 which is equal to 2³ and we will have a overflow .

There two main disadvantages in ripple carry adder

• Propagation delay:
  if inputs A and B changes, the sum at its output will not be valid until any carry-input has “rippled” through every full adder in the chain because the MSB of the sum has to wait for any changes from the carry input of the LSB. Consequently, there will be a finite delay before the output of the adder responds to any change in its inputs resulting in a accumulated/propagation delay. This delay can be neglected for 4 to 8 bits but we cannot neglect the delay for higher bits like 32 bits and more.
• Over flow:
  Overflow occurs when the two n bit numbers add together whose sum is greater than or equal to 2ⁿ

To reduce the propagation delay of carry_in we can use Carry Look Ahead Binary Adder

CHISEL: Counter in Chisel

In digital systems counter is plays a main role. Counters are used to keep a track of events , time intervals and no of interrupts etc. . Counter can be programmed in many languages like verilog, c , c++ , java, python, chisel etc. In this post we will see how to program a counter in chisel language.

Design a counter which starts counting from 0 till 9 and reset to 0 once it counts till 9.

val cntSpace = RegInit (0.U (8.U))—> defines a 8 bit register which initialize to 0 upon reset signal
cntSpace := Mux( cntSpace ===9.U , 0.U, cntSpace + 1.U)

:= ——> update register
When the cntSpace reaches to 9, it will initialize to 0 otherwise the cntSpace will be incremented by one

scan cell, scan chain

Scan cell is one of the DFT technique , to test the sequential circuits in the Asic/Soc design. Normal D flip flop are converted to scan flip flop, if the tool meets the following criteria

• Clock of the flip flop must be controllable
• The set/reset of the flops must be inactive during the shift mode.

Once the all the flops in the design meet the above two rules the tool will convert the d flops to scan flops by adding a mux as shown in figure above. Then the tools will stitch the scan cells into a scan chain according to the design requirements.

When Scan Enable is 0 (SE=0), all the scan chains in the design will be disconnected and the flops are connected to comb. logic

When Scan Enable is 1 (SE=1) , combinational logic will be bypassed and all scan cells will be connected to form a scan chain

When SE=1 , patterns are loaded to the scan chains and the data from the comb logic are captured when SE=0

scan chain REORDERING , why it is required

Scan chain reordering is an optimization technique to ensure scan chains are connected in more efficient way – based upon the placement of the flip-flops. At initial stage , we donot have the placement information, so we just stitch the flops register by register. The tools will stitch the flops randomly to form a scan chain before placement. For proper understanding flops are numbered and two scan chains are stitched in the screen shot shown below.

But after placement it might be possible that the two flops stitched at initial stage of a different block sits far from each other when the placement is done. So if we keep the same scan chain order, we will face the placement congestion and timing congestion and more routing resources are required.

We can see from above screenshot, depending on the timing and placement congestion flops are placed at different locations when compared to before placement figure. This results in usage of more resources, space congestion increases and also timing violations. By reordering the scan cells in the scan chain we can reduce the congestion

In order to avoid the congestion before placement we have to follow the below steps

• Disconnect the scan chain in the designing.
• Based on the timing and congestion the tool optimizes the standard cells
• Once the placement was done, reordering of scan chains are done based on the timing and placement congestion in design by maintaining the same number of scan cells .

SCANDEF file contains the scan chain information of the design and this file need to be read during PnR.

Untestable faults in DFT

Faults list in design are categorized into sub categories. Faults class are mainly divided into

• Testable(TE)–> Faults can be tested by some patterns.
• Untestable(UT)–> Faults foe which no pattern exits to detect the faults

Untestable Faults: Are the faults for which no pattern exit to either detect or possible detect them. These faults cannot cause any functional failures. And so the tools excludes them while calculating the test coverage. Types of Untestable faults are

• Unused (UU)
• Tied (TI)
• Blocked(BL)
• Redundant Faults (RE)

• Unused (UU)
  • Any floating pins not used in the design come under UU faults
  • The unused faults class includes all the faults on circuit unconnected to any observation point

• Tied (TI)
  • This faults includes faults on gates where the point of the faults is tied to a value identical to the fault stuck value

• Blocked (BL)
  • Due to tied logic in the design few faults are blocked and these are categories into Blocked faults. By adding the observable test point we can increase the coverage report.

• Redundant (RE)
  • The faults which are undetectable by the tool by any pattern , are classified as redundant faults

Fault Class Hierarchies in DFT

Faults list in design are categorized into sub categories. Faults class are mainly divided into

• Testable(TE)–> Faults can be tested by some patterns.
• Untestable(UT)–> Faults foe which no pattern exits to detect the faults

• Testable Faults: There are four sub category under TE.
  • DETECTED(DT)
  • POSDET(PD)
  • ATPG UNTESTABLE(AU)
  • UNDETETED(UD)

• Detected(DT): The Faults which are detected during the ATPG process are categories under DT
  • det_simulation(DS): The faults detected when the tools performs simulation
  • det_implication(DI): The faults detected when the tool performs learning analysis
• POSDET(PD): The Possible detected, faults includes all the faults that fault simulation identifies as possible detected
  • posdet_testable(PT): Potentially detectable posdet faults.With higher abort limit we can reduce the number of these faults
  • posdet_untestable(PU): These are proven ATPG untestable and hard undetectable faults.
• ATPG_UNTESTABLE(AU): This fault class includes all the faults for which test generator unable to find the pattern to create a test. Testable faults become ATPG untestable faults because of constraints or limitations, placed on the ATPG tool such as pin constraint or an insufficient sequential depth. This faults may be detectable, if we remove some constraint, or change some limitations on the test generator
• UNDETECTED (UD): This fault class includes the undetected faults that cannot be proven untestable or atpg_untestable
  • uncontrolled(UC)
  • unobserved(UO)
    All the testable faults prior to ATPG are put in the UC category. Faults that remain UC or UO after APTG aborted, which means that with higher abort limit may reduce the UC and UO fault class

Different ways of Digital design representation

A digital design can be represented at various levels from three different angles

• Behavioral
• Structural
• Physical

This can be represented by Y chart

Behavioral Representation

• Specifies how a particular should respond to a given set of inputs
• May be specified by
  -Boolean Equations
  -Tables of input and output values
  -Algorithms written in standard HLL like C/C++
  -Algoriths written in special HDL like verilog or VHDL or CHISEL

Example:

———————————–An Algorithm level of description of carry(Cy)———————————-
module carry (cy, a,b,c);
input a,b,c;
output cy;
assign cy = (a&b)|(a&c)|(b&c);
endmodule

——————————Boolean behavioral specification for carry (cy)————————————
primitive carry (cy,a b,c);
input a,b,c;
output cy;
table
// a b c : cy
   1 1 ? : 1 ;
   1 ? 1 : 1 ;
   ? 1 1 : 1 ;
   0 0 ? : 0 ;
   0 ? 0 : 0 ;
   ? 0 0 : 0 ;
endtable
endprimitive

Structural Representation

• Specifies how components are interconnected
• In general, the description is a list of modules and their interconnects
  – called Netlist
  – can be represented at various levels
• At Structural Level, levels of abstraction are:
  – The module (functional) level
  – The Gate level
  – The switch level
  – The circuit level

Example:
——————————————–Structural Representation—————————————–
module carry (cy , a, b, c);
input a, b, c;
output cy;
wire w1,w2,w3;
  and g1 (w1, a, b);
  and g2 (w2, a, c);
  and g3 (w3, b, c);
  or g4 (cy, w1,w2,w3);
endodule

Physical Representation

• The lowest level of physical specification
  – Photo-mask information required by various processing steps in the fabrication process.
• At the module level, the physical layout for the adder may be defined by a rectangle or polygon, and collection of ports

Example:
———————————————–Physical representation————————————————-
A possible (partial) physical description of 4 bit adder

module adder4 ;
input [3:0] a,b;
input c;
output [3:0] s;
output cy;
boundary [0 0 130 500];
port x[0] aluminum width = 1 origin = [0,35];
port y[0] aluminum width = 1 origin = [0,85];
port c polysilicon width = 2 origin = [70,0];
port s[0] aluminum width = 1 origin = [120,65];

add a0 orgin =[0 , 0];
add a1 orgin =[0 ,120];
endmodule

Design For Testability

DFT means Design for testability, where logic will be implemented or inserted in the core design at RTL stage(Now a days most of the company prefer at RTL stage) or Netlist stage. This test circuit verifies that core design does not have manufacturing defects focusing on circuit structure rather than functional behavior.

Manufacturing defects may include

• Short circuits
• Open interconnects
• Power and ground shorts

Manufacturing defects remain undetected by functional testing and these can cause undesirable behaviour during circuit operation. DFT helps to find the manufactured defects and improves the quality, yield of products.

Now you may wonder what is the use of Functional testing.Functional testing verifies your circuit performs .For example assume that your design is an Half adder circuit , Functional test verifies that circuit performs the addition operation and computes the correct results over the range of patterns