Before implementing the logic, we will have a look at the truth table of the NAND gate and the inverter.
NAND GATE
A
B
O
0
0
1
0
1
1
1
0
1
1
1
0
NOT GATE
A
O
0
1
1
0
Fro the NAND gate truth table we can conclude the following When both the inputs are zero(0) ==> output is 1 (same as inverter) when both the inputs are one(1) ==> output is 0 (same as inverter)
Thus we can implement the not gate by connecting the both inputs together as shown below
There is another way of implementation of inverter using NAND gate , from truth table when input pin A is high (logic one) Nand gate behavious as INVERTER
Before implementing the logic, we will have a look at the truth table of the NOR gate and the inverter.
NOR GATE
A
B
O
0
0
1
0
1
0
1
0
0
1
1
0
NOT GATE
A
O
0
1
1
0
case I: From the NOR truth table we can see that when both the inputs are zero(0) ==> output is 1(same as inverter) both the inputs are one (1) ==> output is 0 (same as inverter)
Case II : second way of implementation of Inverter using Nor Gate.
A digital design can be represented at various levels from three different angles
Behavioral
Structural
Physical
This can be represented by Y chart
Behavioral Representation
Specifies how a particular should respond to a given set of inputs
May be specified by -Boolean Equations -Tables of input and output values -Algorithms written in standard HLL like C/C++ -Algoriths written in special HDL like verilog or VHDL or CHISEL
Example:
———————————–An Algorithm level of description of carry(Cy)———————————- module carry (cy, a,b,c); input a,b,c; output cy; assign cy = (a&b)|(a&c)|(b&c); endmodule
In general, the description is a list of modules and their interconnects – called Netlist – can be represented at various levels
At Structural Level, levels of abstraction are: – The module (functional) level – The Gate level – The switch level – The circuit level
Example: ——————————————–Structural Representation—————————————– module carry (cy , a, b, c); input a, b, c; output cy; wire w1,w2,w3; and g1 (w1, a, b); and g2 (w2, a, c); and g3 (w3, b, c); or g4 (cy, w1,w2,w3); endodule
Physical Representation
The lowest level of physical specification – Photo-mask information required by various processing steps in the fabrication process.
At the module level, the physical layout for the adder may be defined by a rectangle or polygon, and collection of ports
Example: ———————————————–Physical representation————————————————- A possible (partial) physical description of 4 bit adder
Generates the netlist for the register transfer level components
Logic Design
Generate the netlist of Gates/Flip-Flops or Standard cells
Physical Design
Generate the final layout
Manufacturing the chip in Fabrication unit
Some more Intermediate steps are required during the Design flow.
Simulation for Verification
It should be carried out at various levels, which includes: Logic level, Switch level, Circuit level
Formal Verification
Logical equivalence check will be carried at various levels, to check core design was not disturbed.
LEC/Formal Verification on the design was done between -RTL and Synthesised Netlist -Synthesized Netlist and DFT inserted Netlist -MBIST Inserted Netlsit and Synthesized Netlist, etc
In digital design, register are the basic elements which are used widely. Chisel provides a register , which is collection of D Flip Flops. The register is connected to a clock and the output of the register updates on every rising edge. When an initialization value is provided at the declaration of thr register, it uses a synchronous reset connected to reset signal. A register can be any chisel type that can be represented as a collection of bits.
Below line defines an 8 bit register, initialized with 0 at reset: val reg = RegInit(0.U(8.W))
An input is connected to the register with the := update operator and the output of the register can be used just with the name in an expression
reg := d val q = reg
A register can also be connected to its input at the definition:
val nextReg = RegNext(d)
A register can also be initialized during the definition:
MBIST( Memory Built In Self Test) is implemented to test memories in the design for different types of faults. MBIST contains the processor and wrapper which will be wrapped arround the memories.The MBIST processor controlls the wrapper and generates various control signals during the memory testing. A design may have multiple processors depending on the number of memories, memory size, power, frequency and memory placement.
Memories which are placed near by are grouped together and controlled by single processor. Thereofore, we need the memory placement info to group the memories under a controller and this info was given to the DFT team in the form of DEF and floorplan snapshot. This info will be given by PD/PNR team.
What happens if memories are not grouped properly? If memories are not grouped properly according to their physical location i.e memories under same processors are sitting at different corners. This will lead to MBIST logic spreading, which impacts on MBIST timing during the STA due to long paths or increase in congestion due to lots of criss-cross while implementing the PNR and also increases the unneccesary power consumtption.
A multiplexer is a circuit which selects between the input signals depending on select signal. In basic form of multipexer (2:1 mux) selects between two signals. Below fig represents the 2:1 multiplexer , depending upon the sel signal y will represent the input signal a or b
A multiplexer can be designed using logic gates. As the multiplexer is used more frequently in digital desgin, chisel provides the function called MUX
val results = Mux(sel , a, b)
where a is selected when sel is true, otherwise b is selected, type of sel is a chisel Bool. The inputs a and b can be any chisel base type or aggregate (bundlers or vectors) as long as they are same type
A Bundle to group signals of different types. A Vec to represents an indexable collection of signals of the same type
During the DFT validation patterns are used which are generated during ATPG stage, even these patterns(in Still, wgl format) are used to test a chip on ATE. As there is limitation on memory of the ATE, size of the patterns generated must be with in the memory limit of ATE. Thus we have to reduce the patterns count/pattern volume for a design without losing the coverage. Few of the technique are
For pattern reduction, First step is chain balancing. During scan insertion scan chains present in the design must be balanced(of equal length), so that tool will insert the less dummy patterns for reaching a required flip flop.
we can also include compression on the chains. This means if we are having the compression factor of 2 then your 1 scan chain will get divided into 2 inside the device reducing your chain length (flops per scan chain), thus less patterns are required.
compression ratio: The compression ratio in DFT used to reduce the TESTER Application time and TESTER data volume(size of pattern).
