Gate level Modelling

The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design

Gate primitives are predefined in Verilog, which are ready to use. They are instantiated like modules. There are two classes of gate primitives: Multiple input gate primitives and Single input gate primitives.
Multiple input gate primitives include and, nand, or, nor, xor, and xnor. These can have multiple inputs and a single output. They are instantiated as follows:

// Two input AND gate.
and and_1 (out, in0, in1);

// Three input AND gate.
and and_2 (out, in0, in1, in2);

// Two input OR gate.
or or_1 (out, in0, in1);

// Four input NOR gate.
or or_2 (out, in0, in1, in2, in3);

// Five input XOR gate.
xor xor_1 (out, in0, in1, in2, in3, in4);

// Two input XNOR gate.
xnor and_1 (out, in0, in1);

Single input gate primitives include not, buf, notif1, bufif1, notif0, and bufif0. These have a single input and one or more outputs. Gate primitives notif1, bufif1, notif0, and bufif0 have a control signal. The gates propagate if only control signal is asserted, else the output will be high impedance state (z). They are instantiated as follows:

// Inverting gate.
not not_1 (out, in);

// Two output buffer gate.
buf buf_1 (out0, out1, in);

// Single output Inverting gate with active-high control signal.
notif1 notif1_1 (out, in, ctrl);

// Double output buffer gate with active-high control signal.
bufif1 bufif1_1 (out0, out1, in, ctrl);

// Single output Inverting gate with active-low control signal.
notif0 notif0_1 (out, in, ctrl);

// Single output buffer gate with active-low control signal.
bufif0 bufif1_0 (out, in, ctrl);

Gate delays

Gate Delays

In Verilog, a designer can specify the gate delays in verilog code. This helps the designer to get a real time behavior of the logic circuit.

Rise delay: It is equal to the time taken by a gate output transition to 1, from another value 0, x, or z.

Fall delay: It is equal to the time taken by a gate output transition to 0, from another value 1, x, or z.

Turn-off delay: It is equal to the time taken by a gate output transition to high impedance state, from another value 1, x, or z.

• If the gate output changes to x, the minimum of the three delays is considered.
• If only one delay is specified, it is used for all delays.
• If two values are specified, they are considered as rise, and fall delays.
• If three values are specified, they are considered as rise, fall, and turn-off delays.
• The default value of all delays is zero.

and #(5) and_1 (out, in0, in1);
// All delay values are 5 time units.

and #(3,4,5) nand_1 (out, in0, in1);
// rise delay = 3, fall delay = 4, and turn-off delay = 5.

and #(3,4) or_1 (out, in0, in1);
// rise delay = 3, fall delay = 4, and turn-off delay = min(3,4) = 3.

There is another way of specifying delay times in verilog. Min:Typ:Max values for each delay. This helps designer to have a much better real time experience of design simulation, as in real time logic circuits the delays are not constant. The user can choose one of the delay values using +maxdelays, +typdelays, and +mindelays at run time. The typical value is the default value.

and #(4:5:6) and_1 (out, in0, in1);
// For all delay values: Min=4, Typ=5, Max=6.

and #(3:4:5,4:5:6,5:6:7) nand_1 (out, in0, in1);
// rise delay: Min=3, Typ=4, Max=5, fall delay: Min=4, Typ=5, Max=6, turn-off delay: Min=5, Typ=6, Max=7.

In the above example, if the designer chooses typical values, then rise delay = 4, fall delay = 5, turn-off delay = 6.

Basics : Data Types III

Vectors

Vectors can be a net or reg data types. They are declared as [high:low] or [low:high], but the left number is always the MSB of the vector.

wire [7:0] vs; // vs[7] is the MSB.
reg [0:15] vs_1; // vs_1[15] is the MSB.

In the above examples: If it is written as vs[5:2], it is the part of the entire vector which contains 4 bits in order: vs[5], vs[4], vs[3], vs[2].

Similarly vs_1[0:7], means the first half part of the vecotr vs_.1
Vector parts can also be specified in a different way:
vector_name[start_bit+:width] : part-select increments from start_bit in above example: vs_1[0:7] is same as vs_1[0+:8].

vector_name[start_bit-:width] : part-select decrements from start_bit in above example: vs[5:2] is same as vs[5-:4].

Arrays

Arrays of reg, integer, real, time, and vectors are allowed. Arrays are declared as follows:

reg vs1[0:7];
real vs3[15:0];
wire [0:3] vs4[7:0]; // Array of vector
integer vs5[0:3][6:0]; // Double dimensional array

Strings

Strings are register data types. For storing a character, we need a 8-bit register data type. So if you want to create string variable of length n. The string should be declared as register data type of length n*8.

reg [8*8-1:0] vs_1; // vs_1 is a string of length 8.

Time Data Types

Time data type is declared using the keyword time. These are generally used to store simulation time. In general it is 64-bit long.

time vs_1;
Vs_1 = $time; // assigns current simulation time to vs_1.

Basics : Data types II

Integers

Integer is a register data type of 32 bits. The only difference of declaring it as integer is that, it becomes a signed value. When you declare it as a 32 bit register (array) it is an unsigned value. It is declared using the keyword integer.

Real Number

Real number can be declared using the keyword real. They can be assigned values as follows:
real VS;

VS = 1.234; // Decimal notation.
VS = 3e4; // Scientific notation.

Parameter

Parameters are the constants that can be declared using the keyword parameter. Parameters are in general used for customization of a design. Parameters are declared as follows:

parameter vs = 123; // vs is a constant with value 123.

Keyword defparam can be used to change a parameter value at module instantiation. Keyword localparam is usedd to declare local parameters, this is used when their value should not be changed.

Basics : Data Types I

Value Set

The Verilog HDL value set consists of four basic values:

• 0 – represents a logic zero, or a false condition.
• 1 – represents a logic one, or a true condition.
• x – represents an unknown logic value.
• z – represents a high-impedance state.

The values 0 and 1 are logical complements of one another. Almost all of the data types in the Verilog HDL store all four basic values.

Nets

Nets are used to make connections between hardware elements. Nets simply reflect the value at one end(head) to the other end(tail). It means the value they carry is continuously driven by the output of a hardware element to which they are connected to. Nets are generally declared using the keyword wire. The default value of net (wire) is z. If a net has no driver, then its value is z.

Register

Registers are data storage elements. They hold the value until they are replaced by some other value. Register doesn’t need a driver, they can be changed at anytime in a simulation. Registers are generally declared with the keyword reg. Its default value is x. Register data types should not be confused with hardware registers, these are simply variables.

Synchronous Reset and Asynchronous Reset

A Reset is required to initialize a hardware design for system operation and to force an value into a known state for simulation.

A reset simply changes the state of the device to a user defined state. There are two types of reset, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active/negative edge of the clock.

Advantages:

• The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.
• Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.
• Synchronous resets provide some filtering for the reset signal such that it is not effected by glitches, unless they occur right at the clock edge. A synchronous reset is recommended for some types of designs where the reset is generated by a set of internal conditions. As the clock will filter the logic equation glitches between clock edges.

Disadvantages:

• The problem in this topology is with reset assertion. If the reset signal is not long enough to be captured at active clock edge (or the clock may be slow to capture the reset signal), it will result in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset pulse is wide enough to be present during the active clock edge.
• Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the reset signal from any other data signal. So proper care has to be taken with logic synthesis, else the reset signal may take the fastest path to the flip-flop input there by making worst case timing hard to meet.
• In some power saving designs the clocked is gated. In such designed only asynchronous reset will work.
• Faster designs that are demanding low data path timing, can not afford to have extra gates and additional net delays in the data path due to logic inserted to handle synchronous resets.

Asynchronous Reset

An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the clock signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.

Advantages:

• High speeds can be achieved, as the data path is independent of reset signal.
• Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.
• As in synchronous reset, no work around is required for logic synthesis.

Disadvantages:

• The problem with this type of reset occurs at logic de-assertion rather than at assertion like in synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.
• Spurious resets can happen due to reset signal glitches.

CHISEL : Vec

A Vec in chisel represents a collections signal (same type). These are similar to the array data structures in other languages. Each element in Vec can be accessed by an index. A Vec will be created by calling a constructor with two parameters:

• The number of elements
• The type of the elements

The combinations vec must be wrap into a wire.
val vs = Wire(Vec(3 , UInt(4.W)))

Individual elements of the vecot can be accessed by index
vs(0) := 1.U
vs(1) := 2.U
vs(2) := 3.U

A vector wrapped into a Wire is multiplexer. We can also wrap the vec into register to define the array of registers as shown below
val regfile = Reg(Vec(32, UInt(32.W))
The elements of that register are accessed by index
val idx = 1.U(2.W)
val dout = regfile(idx)

We can freely mix bundles and vectors, as shown below

val vecBundle = Wire(Vec(8, new vlsiscape() ) ) —> vlsispace() was a bundle defined