Utilisation Factor

Utilization factor gives us information how much area must be occupied by the standard cell. As we increase the utilization factor , total area of the chip or block will be decreased. Let us discuss how the total area decreases and total area was

Total Core Area = area occupied by macros+area occupied by standard cell+ empty area

UF  is defined as (area occupied by the standard cell)/(Total Core Are) and the UF is varied from .3 to .8 . In  industry mostly they will go with utilization factor of 0.7 -0.8

Assume that standard cell occupy 80mm area, all macros in the design occupy 30mm area

• Utilization Factor be 70% means in the core area there should be 30% of free space for future use.
  std. cell area =80mm
  All macros area = 30mm
  Free space area =35 mm
  Total Core Area= 80+30+35 =145mm
  
  And this explained properly in below figure.

• Utilization Factor be 80% means in the core area there should be 20% of free space for future use
  std. cell area =80mm
  All macros area = 30mm
  Free space area =20 mm
  Total Core Area= 80+30+20 = 130mm

we can observe that area of the core decreases if we increase the utilization factor of the block or design

Full Adder

For three bit additions, full adder is used. First step in designing the full Adder circuit is to have truth table. Before that let see the binary addition rules.

Truth Table for Full Adder

Using the k-map, we can get the optimised Boolean expression for sum and carry.
Boolean expression for sum

Boolean Expression for carry

From the above booleaan expression , we can Implement of sum and carry as shown below

How to remove maximum fan out violation for a cell?

Fan-Out of the gate is defined as number of gate inputs it can drive. Every cell/gate will have limitations and we can get the maximum fan limits from LIB file which are provided by vendor or foundry. If Fan out violation occurs for a design or on pin, we can remove the violation by inserting a buffer. 

For example, consider a two input OR gate which has a max fan out limit of 3. Assume in a design this OR gate is connected to 5 loads thus violating the Fan out violation. Violation can be removed by inserting a buffer with fan-out more than 3 as shown below. After inserting the buffer, the OR gate will have a fan-out of 3 which is within the limits.

       

                                            Fig 1 : Fan out of OR gate with out buffer

                              Fig 2 : OR gate with buffer

Target Libraries, Link Libraries, Physical Libraries

Traget Library:

The target libraries are the technology library needed to map to design during synthesis. we have to specify the target library with the pointer variable traget_library.

set target_library {“…………..” “…….”}

Link Library:

The link libraries are the technology library used to describe the function of mapped cells prior to opitimization and these are specified with the variable pointer link_library.

set link_library {“____.db” “___.db”

Physical Library:

The physical libraries are the technology library includes the physical design rules and physical view of the standard cells and these are specified with the pointer variable physical_library.

set physical_library {“____.pdb” “____.pdb”}

Perl Series III

How to remove the repeated words in a line, like shown in file below

===============================

vlsispace = "bin/trail/world", "bin/drive/space", "usr/bin/vlsi", "bin/trail/world";

string1 = "bangalore", "chennai", "newyork", "bangalore";

fruit = "apple", "orange", "grape","apple"; 

==================================

In above file few words are repeated in each line and those extra words need to be removed from the lines

First using grep expression try to capture the line and then split the pattern using a split command. This step will convert the string to a array format .
@fields = split(/delimiter/, “pattern”);
Next step try to remove the repeated word in the array. Finally once all the words are unique, join the array to string with the delimiter that was used to split the string. Join command is used to join the words in array
$string=join(“delimiter”,@array)

There are many ways to write the logic and one of the way is given below

==========================================================

#!/usr/bin/perl

open(rh,"","new_file") or die "couldnt open the file, $!;

foreach $line() {

if($line =~/(\".*\");$){

@fields split(/, /,$1);

my %hashes;

my @unique;

foreach my $value(@fields){

if(!$hashes{$value}){

push @unique $value;

$hashes{$value}=1;

}}

$string = join(", ",@unique);

print wh "$string;\n";

}

else {

print wh $line;

}}

close(wh);

close(rh);

==========================================================

This perl scprit will remove the repeated word from the line and prints a new file with a unique word in a line.

Half adder

Adder is one of the important combinational circuit to perform the Arithmetic Logical operations.

Half Adder:
A half adder is used to add two single digit binary number. First step in designing the Half Adder circuit is to have truth table. Before that let see the binary addition rules.

Truth Table:

Using the k-map, we can get the optimised Boolean expression  for sum and carry.
Boolean expression for sum

Boolean expression for carry

From above equations , the Half adder circuit implemented as below

                                                      Half Adder

Why NAND gate is preffered over NOR gate

 NAND gates are preferred over NOR gates, because of below factors

• Delay offered by NAND gate is less than NOR gate
• Also NAND gate takes less size.
• Low to high and high to low time are more symmentrical in NAND based design than in NOR based design

Before understanding why NAND gate offers less delay compare to NOR gate, we need to understand the pmos and nmos in circuit level and also different delays.
RC equivalent circuit of nmos and pmos with width k is shown in fig 1.

                                                    Fig 1: NMOS and PMOS

Lets us analyse the rc model of inverter (with k_n=1 and k_p=2) which is connected to another inverter of same k_n and k_p value as shown in below fig 2.

Have you noticed width of pmos(k_p) is twice the nmos(k_n), what could be the reason?

In inverter nmos and pmos are connected in series and therefore current through the pmos must be equal to nmos. As mobility of holes are less and offers more resistance, thus to increase the flow of holes channel width of pmos is made twice that of nmos channel width. The elmore delay of the previous ciruit is show below and from this circuit we can calculate all the delays of circuit.

                     Fig 3: RC model of two inverters connected back to back

Delay of any device can expressed as sum of parasitic delay and effort delay/stage effort that depends on complexity and fan-out of the gate
d=p+f 
p————–is the delay of the gate/device when no load is attached.
f—————is the effort delay
f=gh
The complexity is represented by the logical effort, g and this defined as ratio of input capacitance of a gate to the input capacitance of an inverter that as same drive strength (i.e. delivers same current).

Electrical effort is denoted by h, If the load does not contain identical copies of the gate, the electrical effort can be computed as
h = C_load / C_driver
C_load is the capacitance of the external load
C_driver is the driving capacitence of the gate

Now let us consider a two inputs NAND gate and NOR gate , both drives a same external load(C_out =4). Parasitic delay for inverter, NOR, NAND gates approximately equal to number of inputs. Therefore parasitic delay for 2 i/ps NAND and NOR gates are approximately equal to 2 and this delay increases as the no of inputs increase. Assume both NAND and NOR gate have same driving capacity( C_driver =4) and drives same load capacity ( C_load =12) , then electricl effort(h) for both gates will be equal to 3.

The logical effort the gates are follows

                                      Fig 4 : NAND Gate

                                 

                             

                                             Fig 5: Nor Gate

                                              

Delay offer by NOR gate is 7ns which is more than the delay offered by NAND gate.Thus the circuits design with NAND gate offers less delay compared with the ciruit design with NOR gate and therefore as a engineer we need to prefer NAND gate over NOR gate in circuit designing.