CHISEL

Chisel (Constructing Hardware in a Scala Embedded Language)

Is a new hardware language which made open source by UC Berkeley. Chisel supports the advance hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel provides the flexibility of concepts like object orientation, functional programming, parameterized types and type inference over the VHDL or Verilog hardware languages. Chisel adds hardware construction primitives to the scala programming language, providing designers with power of a modern programming language to write complex, prameterizable circuit generators that produce sythesizble Verilog. With single chisel code, we can generate a high-speed C++ based cycle –accurate software simulator, or low-level Verilog design for ASIC or FPGA for synthesis, place and route.

Chisel is powered by FIRRTL (highly parameterized generators and layered domain-specific hardware languages), a hardware complier that performs optimization of chisel-generated circuits.
Steps involved to generate the Verilog from chisel code

1. The Chisel stage/Font-end compiles chisel to a circuit intermediate representation called FIRRTL(highly parameterized generators and layered domain-specific hardware languages
2. FIRRTL stage/ mid-end then optimizes FIRRTL and then applies user custom transformations
3. Finally the Verilog stage/Backend generated the Verilog based on the optimized FIRRTL.

Utilisation Factor

Utilization factor gives us information how much area must be occupied by the standard cell. As we increase the utilization factor , total area of the chip or block will be decreased. Let us discuss how the total area decreases and total area was

Total Core Area = area occupied by macros+area occupied by standard cell+ empty area

UF  is defined as (area occupied by the standard cell)/(Total Core Are) and the UF is varied from .3 to .8 . In  industry mostly they will go with utilization factor of 0.7 -0.8

Assume that standard cell occupy 80mm area, all macros in the design occupy 30mm area

• Utilization Factor be 70% means in the core area there should be 30% of free space for future use.
  std. cell area =80mm
  All macros area = 30mm
  Free space area =35 mm
  Total Core Area= 80+30+35 =145mm
  
  And this explained properly in below figure.

• Utilization Factor be 80% means in the core area there should be 20% of free space for future use
  std. cell area =80mm
  All macros area = 30mm
  Free space area =20 mm
  Total Core Area= 80+30+20 = 130mm

we can observe that area of the core decreases if we increase the utilization factor of the block or design

Full Adder

For three bit additions, full adder is used. First step in designing the full Adder circuit is to have truth table. Before that let see the binary addition rules.

Truth Table for Full Adder

Using the k-map, we can get the optimised Boolean expression for sum and carry.
Boolean expression for sum

Boolean Expression for carry

From the above booleaan expression , we can Implement of sum and carry as shown below

How to remove maximum fan out violation for a cell?

Fan-Out of the gate is defined as number of gate inputs it can drive. Every cell/gate will have limitations and we can get the maximum fan limits from LIB file which are provided by vendor or foundry. If Fan out violation occurs for a design or on pin, we can remove the violation by inserting a buffer. 

For example, consider a two input OR gate which has a max fan out limit of 3. Assume in a design this OR gate is connected to 5 loads thus violating the Fan out violation. Violation can be removed by inserting a buffer with fan-out more than 3 as shown below. After inserting the buffer, the OR gate will have a fan-out of 3 which is within the limits.

       

                                            Fig 1 : Fan out of OR gate with out buffer

                              Fig 2 : OR gate with buffer

Target Libraries, Link Libraries, Physical Libraries

Traget Library:

The target libraries are the technology library needed to map to design during synthesis. we have to specify the target library with the pointer variable traget_library.

set target_library {“…………..” “…….”}

Link Library:

The link libraries are the technology library used to describe the function of mapped cells prior to opitimization and these are specified with the variable pointer link_library.

set link_library {“____.db” “___.db”

Physical Library:

The physical libraries are the technology library includes the physical design rules and physical view of the standard cells and these are specified with the pointer variable physical_library.

set physical_library {“____.pdb” “____.pdb”}

Perl Series III

How to remove the repeated words in a line, like shown in file below

===============================

vlsispace = "bin/trail/world", "bin/drive/space", "usr/bin/vlsi", "bin/trail/world";

string1 = "bangalore", "chennai", "newyork", "bangalore";

fruit = "apple", "orange", "grape","apple"; 

==================================

In above file few words are repeated in each line and those extra words need to be removed from the lines

First using grep expression try to capture the line and then split the pattern using a split command. This step will convert the string to a array format .
@fields = split(/delimiter/, “pattern”);
Next step try to remove the repeated word in the array. Finally once all the words are unique, join the array to string with the delimiter that was used to split the string. Join command is used to join the words in array
$string=join(“delimiter”,@array)

There are many ways to write the logic and one of the way is given below

==========================================================

#!/usr/bin/perl

open(rh,"","new_file") or die "couldnt open the file, $!;

foreach $line() {

if($line =~/(\".*\");$){

@fields split(/, /,$1);

my %hashes;

my @unique;

foreach my $value(@fields){

if(!$hashes{$value}){

push @unique $value;

$hashes{$value}=1;

}}

$string = join(", ",@unique);

print wh "$string;\n";

}

else {

print wh $line;

}}

close(wh);

close(rh);

==========================================================

This perl scprit will remove the repeated word from the line and prints a new file with a unique word in a line.

Half adder

Adder is one of the important combinational circuit to perform the Arithmetic Logical operations.

Half Adder:
A half adder is used to add two single digit binary number. First step in designing the Half Adder circuit is to have truth table. Before that let see the binary addition rules.

Truth Table:

Using the k-map, we can get the optimised Boolean expression  for sum and carry.
Boolean expression for sum

Boolean expression for carry

From above equations , the Half adder circuit implemented as below

                                                      Half Adder