If u ask to do DFT implementation on a design, then what factors do we need consider mainly. While doing the DFT implementation designer need to have some knowledge on tester which will be used for testing IC.
This above facotrs must be considered while implementing the DFT on the design
Design for Testability (DFT) is required to guarantee the product quality, reliability, performances, etc. Design for Testability refers to those design techniques that
There are different methods to implement the DFT Logic for Digital circuits which are listed below
Ad-hoc methods had few disadvantages, and these gives more advantage to Structured methods.
we have came across the scan flip flop, and you may be wondering, what would be the difference between a norml flip flop and a scan flip flop. Below pictorial representation give clear picture about a flop and scan flop.
TM represents Test Mode signal and this signal should be 1 during DFT testing and 0 for functional model.
Chisel uses the boolean algebra operators and arithmetic operators same as in c, java, scala, etc programming languages.
val sel = a & b
The keyword val is part of scala which is used to name the variables that have values that won’t change. And here it is used to name the chisel wire, sel, holding the output of the bitwise and operation. A signal can also first be defined as a Wire of some type. Afterward, we can assign a value to the wire with the ‘:=’ update operator.
val sel = Wire(UInt()))
sel := a & b
Boolean operators
& —– represents bitwise AND operator
val and = a & b
| —– represents bitwise OR operator
val or = a | b
^ —– represents bitwise XOR operator
val xor = a ^ b
~ —– represents bitwise negation
val not = ~a
Arithmetic operations
+ —– Addition operation
val add = a + b
– —– Subtraction operation
val sub = a – b
* —– multiplication operation
val mul = a * b
/ —– division operation
val div = a / b
% —– modulo operation
val mod = a % b
| Operator | Description | Data Types |
| * / % | Multiplication, division, modulus | UInt, SInt |
| + – | Addition, subtraction | UInt, SInt |
| === =/= | Equal, not equal | UInt, SInt, returns Bool |
| > >= <= | Comparison operations | UInt, SInt, returns Bool |
| << >> | Shift left, shift right | UInt, SInt |
| ~ | NOT | UInt, SInt, Bool |
| & | ^ | AND, OR, XOR | UInt, SInt, Bool |
| ! | Logical NOT | Bool |
| && || | Logical AND, OR | Bool |
Below commands must be used in visual mode (ctrl+v)
Recovery Time:
Recovery time is the minmium time that as asynchronous control signal must be stable before the clock active- edge transition. In other words, this check ensures that after the asynchronous signal become inactive, there is adequate time to recover so that the next active clock edge can be effective.
Consider the time as show in below figure, between an asynchronous reset becoming inactive and the clock active edge of a flip-flop. If the active clock edge occurs too soon after the release of reset, in this case the state of the flip-flop may be unknow. Therefore it is required to have minimum time for asynshronus control signal to become stable. Recovery time is similar to setup time.
Removal Time:
Removal time is the minimum length of time that an asynchronous control must be stable after the clock active edge transition. This check ensures that the active clock edge has no effect because the asynchronus control signal remains active until removal time after the active clock edge.
Consider the asynchronous control signal is released(becomes inactive) well after the active clock edge so that the clock edge can have no effect. Similar to hold check, it is minimum path check except that it is on an asynchronous pin of flip flop.
Chisel data types are used to specify the type of values held in the state elements or flowing on wires. Chisel defines the Bundles for making collection of values with named fields (Similar to Structs in other languages and Vecs for indexable collections of values. There are three data types (which represents the vector of bits) to describe the signals, combinational logic, registers.
UInt and SInt extends the Bits data type. The Chisel uses the two’s complement as signed integer representation. Definition for three data types as follows
Bits (8.W) –> an 8 bit width Bits
UInt (8.W) –> an 8 bit width unsigned Integer
SInt (8.W) –> an 8 bit width Signed Integer
Example:
0.U //defines the Unsigned Integer constant of 0
-3.S // defines the Signed Integer constant of -3
We can also define the Integer with width.
7.U(4.W) // defines the Unsigned Integer of width 4
8.S(7.W) // Signed decimal 7 bit literal of type SInt
For constants defined in other bases than decimal, the constant is defined in a string with a preceding h for hexdecimal(base 16), o for octal(base 8), b for binary (base 2). In these case we omit the bit width and the chisel infers the minimum width to fit the constants in, in this below case width 8 will be considered.
“hdf”.U // Hexa decimal representation of 223
“o337”.U // Octal representation of 223
“b1101_1111”.U // Binary representation of 223
Design for Testability circuit is used for controllability and observability of the design. The test logic is inserted in to the main core logic for testing the chip once it is manufactured. Types of DFT logic are
