Simplistic view of ASIC DESIGN flow

Steps in design flow

• Behavioral Design
  • Specifies the functionality of the chip
• Data path Design
  • Generates the netlist for the register transfer level components
• Logic Design
  • Generate the netlist of Gates/Flip-Flops or Standard cells
• Physical Design
  • Generate the final layout
• Manufacturing the chip in Fabrication unit

Some more Intermediate steps are required during the Design flow.

• Simulation for Verification
  • It should be carried out at various levels, which includes: Logic level, Switch level, Circuit level
• Formal Verification
  • Logical equivalence check will be carried at various levels, to check core design was not disturbed.
  • LEC/Formal Verification on the design was done between
    -RTL and Synthesised Netlist
    -Synthesized Netlist and DFT inserted Netlist
    -MBIST Inserted Netlsit and Synthesized Netlist, etc
• Testability analysis and Pattern Generation
  • Required to test the manufactured Devices

chisel:Registers

In digital design, register are the basic elements which are used widely. Chisel provides a register , which is collection of D Flip Flops. The register is connected to a clock and the output of the register updates on every rising edge. When an initialization value is provided at the declaration of thr register, it uses a synchronous reset connected to reset signal. A register can be any chisel type that can be represented as a collection of bits.

Below line defines an 8 bit register, initialized with 0 at reset:
val reg = RegInit(0.U(8.W))

An input is connected to the register with the := update operator and the output of the register can be used just with the name in an expression

reg := d
val q = reg

A register can also be connected to its input at the definition:

val nextReg = RegNext(d)

A register can also be initialized during the definition:

val bothReg = RegNext(d, 0.U)

does knowlege on Location of MEMORIES was important during mbist implementation

MBIST( Memory Built In Self Test) is implemented to test memories in the design for different types of faults. MBIST contains the processor and wrapper which will be wrapped arround the memories.The MBIST processor controlls the wrapper and generates various control signals during the memory testing. A design may have multiple processors depending on the number of memories, memory size, power, frequency and memory placement.

Memories which are placed near by are grouped together and controlled by single processor. Thereofore, we need the memory placement info to group the memories under a controller and this info was given to the DFT team in the form of DEF and floorplan snapshot. This info will be given by PD/PNR team.

What happens if memories are not grouped properly?
If memories are not grouped properly according to their physical location i.e memories under same processors are sitting at different corners. This will lead to MBIST logic spreading, which impacts on MBIST timing during the STA due to long paths or increase in congestion due to lots of criss-cross while implementing the PNR and also increases the unneccesary power consumtption.

CHISEL:multiplexer

A multiplexer is a circuit which selects between the input signals depending on select signal. In basic form of multipexer (2:1 mux) selects between two signals. Below fig represents the 2:1 multiplexer , depending upon the sel signal y will represent the input signal a or b

A multiplexer can be designed using logic gates. As the multiplexer is used more frequently in digital desgin, chisel provides the function called MUX

val results = Mux(sel , a, b)

where a is selected when sel is true, otherwise b is selected, type of sel is a chisel Bool. The inputs a and b can be any chisel base type or aggregate (bundlers or vectors) as long as they are same type

A Bundle to group signals of different types. A Vec to represents an indexable collection of signals of the same type

Techniques to reduce the patterns count without losing coverage

During the DFT validation patterns are used which are generated during ATPG stage, even these patterns(in Still, wgl format) are used to test a chip on ATE. As there is limitation on memory of the ATE, size of the patterns generated must be with in the memory limit of ATE. Thus we have to reduce the patterns count/pattern volume for a design without losing the coverage. Few of the technique are

• For pattern reduction, First step is chain balancing. During scan insertion scan chains present in the design must be balanced(of equal length), so that tool will insert the less dummy patterns for reaching a required flip flop.
• we can also include compression on the chains. This means if we are having the compression factor of 2 then your 1 scan chain will get divided into 2 inside the device reducing your chain length (flops per scan chain), thus less patterns are required.

compression ratio:
The compression ratio in DFT used to reduce the TESTER Application time and TESTER data volume(size of pattern).

What are the deciding factors for a scan desgin

If u ask to do DFT implementation on a design, then what factors do we need consider mainly. While doing the DFT implementation designer need to have some knowledge on tester which will be used for testing IC.

• Number of channels available on the tester
• Memory size of the channel
• Number of scan pins
• The operational frquecny of the tester

This above facotrs must be considered while implementing the DFT on the design

DFT:Ad-hoc methods, Structured methods,Scan cell

Design for Testability (DFT) is required to guarantee the product quality, reliability, performances, etc. Design for Testability refers to those design techniques that

• Enhances testability of device
• Ease ability to generate vectors
• Reduce test time
• Reduce the cost involved during test

There are different methods to implement the DFT Logic for Digital circuits which are listed below

• Ad-hoc methods: Good design practices learnt through experience and those methods are used as guidelines
  • Avoid combinational feedback
  • All flip flops must be initializable
  • Avoid redundant and large fanin gates
  • Provide test control for the signals which are not controllable
  • While designing test logic we have to consider the ATE requirements

Ad-hoc methods had few disadvantages, and these gives more advantage to Structured methods.

• Disdvantages od ad-hoc DFT methods:
  • Experts and tools not always available
  • Test generation is often manual with no guarantee of high fault coverage
  • Design iterations may be necessary

• Structured Methods: Structured DFT provides a more systematic and automatic approach to enhancing design testability. Structured DFT’s goal is to increase the controllability and observability of a circuit. Various methods exist for accomplishing this. The most common is the scan design technique, which modifies the internal sequential circuitry of the design.
  • Scan: In the design all the flip flops are converted to scan flip flop.
  • Boundary Scan
  • Built-in self-test

we have came across the scan flip flop, and you may be wondering, what would be the difference between a norml flip flop and a scan flip flop. Below pictorial representation give clear picture about a flop and scan flop.

TM represents Test Mode signal and this signal should be 1 during DFT testing and 0 for functional model.