scan chain REORDERING , why it is required

Scan chain reordering is an optimization technique to ensure scan chains are connected in more efficient way – based upon the placement of the flip-flops. At initial stage , we donot have the placement information, so we just stitch the flops register by register. The tools will stitch the flops randomly to form a scan chain before placement. For proper understanding flops are numbered and two scan chains are stitched in the screen shot shown below.

But after placement it might be possible that the two flops stitched at initial stage of a different block sits far from each other when the placement is done. So if we keep the same scan chain order, we will face the placement congestion and timing congestion and more routing resources are required.

We can see from above screenshot, depending on the timing and placement congestion flops are placed at different locations when compared to before placement figure. This results in usage of more resources, space congestion increases and also timing violations. By reordering the scan cells in the scan chain we can reduce the congestion

In order to avoid the congestion before placement we have to follow the below steps

• Disconnect the scan chain in the designing.
• Based on the timing and congestion the tool optimizes the standard cells
• Once the placement was done, reordering of scan chains are done based on the timing and placement congestion in design by maintaining the same number of scan cells .

SCANDEF file contains the scan chain information of the design and this file need to be read during PnR.

Untestable faults in DFT

Faults list in design are categorized into sub categories. Faults class are mainly divided into

• Testable(TE)–> Faults can be tested by some patterns.
• Untestable(UT)–> Faults foe which no pattern exits to detect the faults

Untestable Faults: Are the faults for which no pattern exit to either detect or possible detect them. These faults cannot cause any functional failures. And so the tools excludes them while calculating the test coverage. Types of Untestable faults are

• Unused (UU)
• Tied (TI)
• Blocked(BL)
• Redundant Faults (RE)

• Unused (UU)
  • Any floating pins not used in the design come under UU faults
  • The unused faults class includes all the faults on circuit unconnected to any observation point

• Tied (TI)
  • This faults includes faults on gates where the point of the faults is tied to a value identical to the fault stuck value

• Blocked (BL)
  • Due to tied logic in the design few faults are blocked and these are categories into Blocked faults. By adding the observable test point we can increase the coverage report.

• Redundant (RE)
  • The faults which are undetectable by the tool by any pattern , are classified as redundant faults

Fault Class Hierarchies in DFT

Faults list in design are categorized into sub categories. Faults class are mainly divided into

• Testable(TE)–> Faults can be tested by some patterns.
• Untestable(UT)–> Faults foe which no pattern exits to detect the faults

• Testable Faults: There are four sub category under TE.
  • DETECTED(DT)
  • POSDET(PD)
  • ATPG UNTESTABLE(AU)
  • UNDETETED(UD)

• Detected(DT): The Faults which are detected during the ATPG process are categories under DT
  • det_simulation(DS): The faults detected when the tools performs simulation
  • det_implication(DI): The faults detected when the tool performs learning analysis
• POSDET(PD): The Possible detected, faults includes all the faults that fault simulation identifies as possible detected
  • posdet_testable(PT): Potentially detectable posdet faults.With higher abort limit we can reduce the number of these faults
  • posdet_untestable(PU): These are proven ATPG untestable and hard undetectable faults.
• ATPG_UNTESTABLE(AU): This fault class includes all the faults for which test generator unable to find the pattern to create a test. Testable faults become ATPG untestable faults because of constraints or limitations, placed on the ATPG tool such as pin constraint or an insufficient sequential depth. This faults may be detectable, if we remove some constraint, or change some limitations on the test generator
• UNDETECTED (UD): This fault class includes the undetected faults that cannot be proven untestable or atpg_untestable
  • uncontrolled(UC)
  • unobserved(UO)
    All the testable faults prior to ATPG are put in the UC category. Faults that remain UC or UO after APTG aborted, which means that with higher abort limit may reduce the UC and UO fault class

Implement the inverter using nand/NOR gate

Before implementing the logic, we will have a look at the truth table of the NAND gate and the inverter.

NAND GATE

A	B	O
0	0	1
0	1	1
1	0	1
1	1	0

NOT GATE

A	O
0	1
1	0

Fro the NAND gate truth table we can conclude the following
When both the inputs are zero(0) ==> output is 1 (same as inverter)
when both the inputs are one(1) ==> output is 0 (same as inverter)

Thus we can implement the not gate by connecting the both inputs together as shown below

There is another way of implementation of inverter using NAND gate , from truth table when input pin A is high (logic one) Nand gate behavious as INVERTER

Before implementing the logic, we will have a look at the truth table of the NOR gate and the inverter.

NOR GATE

A	B	O
0	0	1
0	1	0
1	0	0
1	1	0

NOT GATE

A	O
0	1
1	0

case I:
From the NOR truth table we can see that when
both the inputs are zero(0) ==> output is 1(same as inverter)
both the inputs are one (1) ==> output is 0 (same as inverter)

Case II :
second way of implementation of Inverter using Nor Gate.

Different ways of Digital design representation

A digital design can be represented at various levels from three different angles

• Behavioral
• Structural
• Physical

This can be represented by Y chart

Behavioral Representation

• Specifies how a particular should respond to a given set of inputs
• May be specified by
  -Boolean Equations
  -Tables of input and output values
  -Algorithms written in standard HLL like C/C++
  -Algoriths written in special HDL like verilog or VHDL or CHISEL

Example:

———————————–An Algorithm level of description of carry(Cy)———————————-
module carry (cy, a,b,c);
input a,b,c;
output cy;
assign cy = (a&b)|(a&c)|(b&c);
endmodule

——————————Boolean behavioral specification for carry (cy)————————————
primitive carry (cy,a b,c);
input a,b,c;
output cy;
table
// a b c : cy
   1 1 ? : 1 ;
   1 ? 1 : 1 ;
   ? 1 1 : 1 ;
   0 0 ? : 0 ;
   0 ? 0 : 0 ;
   ? 0 0 : 0 ;
endtable
endprimitive

Structural Representation

• Specifies how components are interconnected
• In general, the description is a list of modules and their interconnects
  – called Netlist
  – can be represented at various levels
• At Structural Level, levels of abstraction are:
  – The module (functional) level
  – The Gate level
  – The switch level
  – The circuit level

Example:
——————————————–Structural Representation—————————————–
module carry (cy , a, b, c);
input a, b, c;
output cy;
wire w1,w2,w3;
  and g1 (w1, a, b);
  and g2 (w2, a, c);
  and g3 (w3, b, c);
  or g4 (cy, w1,w2,w3);
endodule

Physical Representation

• The lowest level of physical specification
  – Photo-mask information required by various processing steps in the fabrication process.
• At the module level, the physical layout for the adder may be defined by a rectangle or polygon, and collection of ports

Example:
———————————————–Physical representation————————————————-
A possible (partial) physical description of 4 bit adder

module adder4 ;
input [3:0] a,b;
input c;
output [3:0] s;
output cy;
boundary [0 0 130 500];
port x[0] aluminum width = 1 origin = [0,35];
port y[0] aluminum width = 1 origin = [0,85];
port c polysilicon width = 2 origin = [70,0];
port s[0] aluminum width = 1 origin = [120,65];

add a0 orgin =[0 , 0];
add a1 orgin =[0 ,120];
endmodule

Simplistic view of ASIC DESIGN flow

Steps in design flow

• Behavioral Design
  • Specifies the functionality of the chip
• Data path Design
  • Generates the netlist for the register transfer level components
• Logic Design
  • Generate the netlist of Gates/Flip-Flops or Standard cells
• Physical Design
  • Generate the final layout
• Manufacturing the chip in Fabrication unit

Some more Intermediate steps are required during the Design flow.

• Simulation for Verification
  • It should be carried out at various levels, which includes: Logic level, Switch level, Circuit level
• Formal Verification
  • Logical equivalence check will be carried at various levels, to check core design was not disturbed.
  • LEC/Formal Verification on the design was done between
    -RTL and Synthesised Netlist
    -Synthesized Netlist and DFT inserted Netlist
    -MBIST Inserted Netlsit and Synthesized Netlist, etc
• Testability analysis and Pattern Generation
  • Required to test the manufactured Devices

chisel:Registers

In digital design, register are the basic elements which are used widely. Chisel provides a register , which is collection of D Flip Flops. The register is connected to a clock and the output of the register updates on every rising edge. When an initialization value is provided at the declaration of thr register, it uses a synchronous reset connected to reset signal. A register can be any chisel type that can be represented as a collection of bits.

Below line defines an 8 bit register, initialized with 0 at reset:
val reg = RegInit(0.U(8.W))

An input is connected to the register with the := update operator and the output of the register can be used just with the name in an expression

reg := d
val q = reg

A register can also be connected to its input at the definition:

val nextReg = RegNext(d)

A register can also be initialized during the definition:

val bothReg = RegNext(d, 0.U)