Basics : Data Types I

Value Set

The Verilog HDL value set consists of four basic values:

• 0 – represents a logic zero, or a false condition.
• 1 – represents a logic one, or a true condition.
• x – represents an unknown logic value.
• z – represents a high-impedance state.

The values 0 and 1 are logical complements of one another. Almost all of the data types in the Verilog HDL store all four basic values.

Nets

Nets are used to make connections between hardware elements. Nets simply reflect the value at one end(head) to the other end(tail). It means the value they carry is continuously driven by the output of a hardware element to which they are connected to. Nets are generally declared using the keyword wire. The default value of net (wire) is z. If a net has no driver, then its value is z.

Register

Registers are data storage elements. They hold the value until they are replaced by some other value. Register doesn’t need a driver, they can be changed at anytime in a simulation. Registers are generally declared with the keyword reg. Its default value is x. Register data types should not be confused with hardware registers, these are simply variables.

Synchronous Reset and Asynchronous Reset

A Reset is required to initialize a hardware design for system operation and to force an value into a known state for simulation.

A reset simply changes the state of the device to a user defined state. There are two types of reset, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active/negative edge of the clock.

Advantages:

• The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.
• Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.
• Synchronous resets provide some filtering for the reset signal such that it is not effected by glitches, unless they occur right at the clock edge. A synchronous reset is recommended for some types of designs where the reset is generated by a set of internal conditions. As the clock will filter the logic equation glitches between clock edges.

Disadvantages:

• The problem in this topology is with reset assertion. If the reset signal is not long enough to be captured at active clock edge (or the clock may be slow to capture the reset signal), it will result in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset pulse is wide enough to be present during the active clock edge.
• Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the reset signal from any other data signal. So proper care has to be taken with logic synthesis, else the reset signal may take the fastest path to the flip-flop input there by making worst case timing hard to meet.
• In some power saving designs the clocked is gated. In such designed only asynchronous reset will work.
• Faster designs that are demanding low data path timing, can not afford to have extra gates and additional net delays in the data path due to logic inserted to handle synchronous resets.

Asynchronous Reset

An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the clock signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.

Advantages:

• High speeds can be achieved, as the data path is independent of reset signal.
• Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.
• As in synchronous reset, no work around is required for logic synthesis.

Disadvantages:

• The problem with this type of reset occurs at logic de-assertion rather than at assertion like in synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.
• Spurious resets can happen due to reset signal glitches.

CHISEL : Vec

A Vec in chisel represents a collections signal (same type). These are similar to the array data structures in other languages. Each element in Vec can be accessed by an index. A Vec will be created by calling a constructor with two parameters:

• The number of elements
• The type of the elements

The combinations vec must be wrap into a wire.
val vs = Wire(Vec(3 , UInt(4.W)))

Individual elements of the vecot can be accessed by index
vs(0) := 1.U
vs(1) := 2.U
vs(2) := 3.U

A vector wrapped into a Wire is multiplexer. We can also wrap the vec into register to define the array of registers as shown below
val regfile = Reg(Vec(32, UInt(32.W))
The elements of that register are accessed by index
val idx = 1.U(2.W)
val dout = regfile(idx)

We can freely mix bundles and vectors, as shown below

val vecBundle = Wire(Vec(8, new vlsiscape() ) ) —> vlsispace() was a bundle defined

CHISEL : Bundle

In Chisel provides two constructs to group related signals

• A Bundle to group signals of different type.
• A Vec represents the collection of signal of same type.

A chisel Bundle groups several signals. The entire bundle can be accessed or individual field can be accessed by their names. User or Designer can define a bundle(collections of signals) by definnig a class which extends Bundle and list the fields as vals within the constructor block

class vlsispace() extends Bundle {
val vlsi = UInt(32.W)
val space = Bool()
}

To access the bundle in following way
val vs = Wire(new vlsispace())
vs.vlsi := 124.U
vs.space := false.B

val a = vs.space

By using the dot we can access the field of the particular constructor, which is commonly used in object oriented programming. A Bundle is similar to struct in C , a record in VHDL or struct in system verilog. A bundle can be referred as a whole as follows

val channel = vs

A bundle may as well contain a vector:

class BundleVec extends Bundle {
val vs = UInt(8.U)
val vector = Vec(4 , UInt(4,W))
}

When we want a register of a bundle type that needs a reset value, we first wire of that bundle and define the values for the bundle elements and then passing the bundle to RegInit:

val initval = Wire( new vlsispcae())
initval.vlsi := 1.U
initval.space := true.B

val channelreg = RegInt(initval)

n bit binary adder or ripple carry adder

By using full adder, a single 1-bit binary adders can be constructed from basic logic gates as shown below

But what if we wanted to add together two n-bit numbers, then n number of 1-bit full adders need to be connected or “cascaded” together to produce a adder known as a Ripple Carry Adder.

Ripple carry adder is simply “n“ number of 1-bit full adders cascaded together with full adder representing a single weighted column in a long binary addition. It is called a ripple carry adder because the carry signals produce a “ripple” effect through the binary adder from LSB to MSB.

Let us consider a three bit full adders to “add” together two 3-bit numbers, the two outputs of the first full adder will provide the first place digit sum (S) of the addition plus a carry-out bit that acts as the carry-in digit of the next binary adder. The second binary adder in the chain also produces a summed output (the 2nd bit) plus another carry-out bit and we can keep adding more full adders to the combination to add larger numbers, linking the carry bit output from the first full binary adder to the next full adder, and so forth. An example of a 3-bit adder is given below.

Let us consider A =4 , B=3, sum of A and B will be 7. In binary addition

There will be a overflow ,If the sum was greater than or equal to 2ⁿ one of the disadvantage in this adder. Let us consider A =4 , B=4, Sum of A and B will be 8 which is equal to 2³ and we will have a overflow .

There two main disadvantages in ripple carry adder

• Propagation delay:
  if inputs A and B changes, the sum at its output will not be valid until any carry-input has “rippled” through every full adder in the chain because the MSB of the sum has to wait for any changes from the carry input of the LSB. Consequently, there will be a finite delay before the output of the adder responds to any change in its inputs resulting in a accumulated/propagation delay. This delay can be neglected for 4 to 8 bits but we cannot neglect the delay for higher bits like 32 bits and more.
• Over flow:
  Overflow occurs when the two n bit numbers add together whose sum is greater than or equal to 2ⁿ

To reduce the propagation delay of carry_in we can use Carry Look Ahead Binary Adder

CHISEL: Counter in Chisel

In digital systems counter is plays a main role. Counters are used to keep a track of events , time intervals and no of interrupts etc. . Counter can be programmed in many languages like verilog, c , c++ , java, python, chisel etc. In this post we will see how to program a counter in chisel language.

Design a counter which starts counting from 0 till 9 and reset to 0 once it counts till 9.

val cntSpace = RegInit (0.U (8.U))—> defines a 8 bit register which initialize to 0 upon reset signal
cntSpace := Mux( cntSpace ===9.U , 0.U, cntSpace + 1.U)

:= ——> update register
When the cntSpace reaches to 9, it will initialize to 0 otherwise the cntSpace will be incremented by one

scan cell, scan chain

Scan cell is one of the DFT technique , to test the sequential circuits in the Asic/Soc design. Normal D flip flop are converted to scan flip flop, if the tool meets the following criteria

• Clock of the flip flop must be controllable
• The set/reset of the flops must be inactive during the shift mode.

Once the all the flops in the design meet the above two rules the tool will convert the d flops to scan flops by adding a mux as shown in figure above. Then the tools will stitch the scan cells into a scan chain according to the design requirements.

When Scan Enable is 0 (SE=0), all the scan chains in the design will be disconnected and the flops are connected to comb. logic

When Scan Enable is 1 (SE=1) , combinational logic will be bypassed and all scan cells will be connected to form a scan chain

When SE=1 , patterns are loaded to the scan chains and the data from the comb logic are captured when SE=0