WHAT IS SYNTHESIS IN DIGITAL DESIGN

 Synthesis

Synthesis: It is a process to map and optimizing higher level HDL description to technology cells (gates, flip flops etc.)

Synthesis Flow Diagram:

HDL Description: This is description of design in Verilog. One has to use subset of constructs as synthesis tools does not support all of them.

Technology Library: This file contains functional description and other information related to area and speed for all the cells of particular technology.

Here "technology" means information about particular process for particular vendor. For example Company X, Standard Cell, 0.18 micron, Y Process, Z Type.

Constraints: This optional file contains information about physical expectations from design. For example speed and area.

Netlist: A netlist is a text file description of a physical connection of components.

Reports: This optional output file contains physical performance of design in terms of speed and area.

Schematic: Some tools provide the facility to view netlist in terms of schematics for better understanding of design and to match the results with the expectations.

Simple example:
Following trivial example explains the Synthesis process. In this example only always procedural statement is used.

module test (out, in1, in2); // behavioral description
  input in1, in2;
  output out;
  reg out;
  reg temp;                 // temporary register

  always@(in1 or in2) begin
    temp = ~in2;
    out = ~in1 ^ temp;  // I am trying to have exor with inverted 
  end                   // inputs
endmodule

after synthesis one gets following "netlist" in verilog. Note that XOR2 is module picked up from technology library. It will be different for different libraries.

module add ( out , in1 , in2 );  // netlist

    output out ;
    input in1 ;
    input in2 ;

    XOR2   instance_name (.Y (out ),.A (in1 ),.B (in2 ) );

endmodule

VERILOG CODE FOR D FLIP FLOP

The Verilog beginners need examples of simple building blocks to learn coding techniques. Now  we will go through different implementation of D FLIP FLOP

=========================================================================

1.Simple D FLIP FLOP 

module dff (data, clock, q);
    // port list
    input   data, clock;
    output  q;

    // reg / wire declaration for outputs / inouts     
    reg     q;

    // logic begins here
    always @(posedge clock) 
        q <= data;
endmodule

========================================================================

2. D Type Flip-flop with asynchronous reset

module dff_async (data, clock, reset, q);

    // port list
    input   data, clock, reset;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // reg / wire declaration for internal signals

    // logic begins here
    always @(posedge clock or negedge reset)
        if(reset == 1'b0)
            q <= 1'b0;
        else 
            q <= data;
endmodule

=======================================================================

3. D Type Flip-flop with Synchronous reset

module dff_sync (data, clock, reset, q);
    // port list
    input   data, clock, reset;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // reg / wire declaration for internal signals

    // logic begins here
    always @(posedge clock) 
        if(reset == 1'b0)
            q <= 1'b0;
        else 
            q <= data;
endmodule

================================================================================

4.D Type Flip-flop with asynchronous reset and clock enable

module dff_cke (data, clock, reset, cke, q);
    // port list
    input   data, clock, reset, cke;
    output  q;

    // reg / wire declaration for outputs / inouts
    reg     q;

    // logic begins here
    always @(posedge clock or negedge reset) 
        if (reset == 0)
            q <= 1'b0;
        else if (cke == 1'b1)
            q <= data;
endmodule

Vlsi Design Styles in Digital Design

Digital Design can be implemented by various design styles. And depending on the market requirement different design styles are used.

• Programmable Logic Design
  • Field Programmable Gate Array (FPGA)
  • Gate Array
• Standard Cell (semi custom design)
• Full Custom Design

• Field Programmable Gate Array (FPGA):
  • Using VHDL or verilog
  • Implementation
    • Placement and Routing
    • BitStream Generation
    • Analyse timing, view layout, simulations etc
• Gate Array: Gate Array design implementation is done with metal design and processing. The implementation requires two-step manufacturing process
  • First phase, which is based on standard masks, results in an array of uncommitted transistors on each GA chips
  • These uncommitted chips can be customized later, which is completed by defining the metal interconnects between the transistor of the array
  • In this chip utilization factor is higher than that of FPGA
  • Chip speed is higher
• Standard Cell or Semi Custom Design:
  • The standard-cells based design is often called semi custom design.
  • The cells are pre-designed for general use and the same cells are utilized in many different chip designs. 
• Full Custom Design
• Full custom design involves creating IC where each individual transistors architecture and interconnections are specified. Designers manually place transistors, resistors,capacitors and other components at the transistor level

STANDARD CELLS IN DIGITAL DESIGN/VLSI

Standard cell are well defined cells which are used in Digital Design more frequently. To name few AND, NOR, NAND, XOR ,etc belongs to standard cell family. All the standard cells from one library will have equal drive strength  and  equal height. Standard cell Architecture is defined based on  cell height which is determined on the basis of the number of trackes , beta ratio, pitch and transistor widths. To attain the similarity amoung the cells and aboid the alignment issues ,standard cells are designed with fixed height

The height of a standard cell can be calculated by considering number of tracks required for power rail, ground rail, I/O pins and routing. Often the standard cells are available in single height and double height. The Double height cells are the high density cells and are used for ultra high speed operations 

STANDARD CELL DESIGN METHODOLOGY

• VDD and GND should be of same height and parallel. Both the power rails used metal M1
• make sure within the cell all the PMOS should occupy top and all NMOS should occupy bottom of the Layout
• Preferred Practice:  Diffusion layer for all the transistor in a row
• All the gates include the gate and substrate

 Layout for any schematic can be drawn in many ways. Layout of INVERTER can be drawn in two different ways.

In the Fig 2 was preferred layout as all the PMOS will be in one level and all the NOMS will be at one level, and also the poly gates are drawn vertical and these are common to nmos and pmos transistors. 

One more layout example with NAND GATE

There are many reasons for choosing the FIG 2 and FIG 3 as most preferred Layout

• Save the Design Area: Both the nwell and pwell are in the same level for all the standard cell, so make a common well which saves lots of areas 
• Easy Placement for APR tool: All the standard cells have the same height and easily can be fit into the standard cell row so make it easy for APR (Automatic Place and Route) to place them. They also have power rails in the same location for all the standard cells, so power rails can also be abutted easily 
• Easy to Route: All the pins of standard cells are in the intersection of horizontal and vertical tracks, So it becomes easy to route them by the APR tool . 

Different Cells in Digital Design

 In any digital design apart from the standard cell , we need to different Physical Cell to minimize the issues in the design. 

• Standard Cells
• Tap Cells
• End cap Cells
• ICG Cells
• DECAP Cells
• Filler Cells
• ESD Clamps
• Tie Cells
• Spare Cells
• Delay Cells
• Metrology Cells

CROSS TALK

Crosstalk noise: noise refers to undesired or unintentional effect between two or more signals that are going to affect the proper functionality of the chip. It is caused by capacitive coupling between neighboring signals on the die. In deep submicron technologies, noise plays an important role in terms of functionality or timing of device due to several reasons.

• Increasing the number of metal layers. For example, 28nm has 7 or 8 metal layers and in 7nm it’s around 15 metal layers.
• Vertically dominant metal aspect ratio it means that in lower technology wire are thin and tall but in higher technology the wire is wide and thin, thus a greater the proportion of the sidewall capacitance which maps into wire to wire capacitance between neighboring wires.
• Higher routing density due to finer geometry means more metal layers are packed in close physical proximity.
• A large number of interacting devices and interconnect.
• Faster waveforms due to higher frequencies. Fast edge rates cause more current spikes as well as greater coupling impact on the neighboring cells.
• Lower supply voltage, because the supply voltage is reduced it leaves a small margin for noise.
• The switching activity on one net can affect on the coupled signal. The effected signal is called the victim and affecting signals termed as aggressors.

There are two types of noise effect caused by crosstalk

• Glitch: when one net is switching and another net is constant then switching signal may cause spikes on the other net because of coupling capacitance (Cc) occur between two nets this is called crosstalk noise.

In fig the positive glitch is induced by crosstalk from rising edge waveform at the aggressor net. The magnitude of glitch depends on various factors.

• Coupling capacitance between aggressor and victim net: greater the coupling capacitance, larger the magnitude of glitch.
• Slew (transition) of the aggressor net: if the transition is more so magnitude of glitch also more. And we know the transition is more because of high output drive strength.
• If Victim net grounded capacitance is small then the magnitude of glitch will be large.
• If Victim net drive strength is small then the magnitude of glitch will be large.

Types of glitches:

• Rise: when a victim net is low (constant 0) and the aggressor net is at a rising edge.

• Fall: when a victim net is high (constant 1) and the aggressor net is at the falling edge.

• Overshoot: when a victim net is high (constant 1)) and the aggressor net is at a rising edge.

• Undershoot: when a victim net is low (constant 0) and the aggressor net is at the falling edge.

Crosstalk delay: 

when both nets are switching or in transition state then switching signal at the victim signal may have some delay or advancement in the transition due to coupling capacitance (Cc) occur between two nets this is called crosstalk delay.
Crosstalk delay depends on the switching direction of aggressor and victim net because of this either transition is slower or faster of the victim net.


Types of crosstalk:
Positive crosstalk: the aggressor net has a rising transition at the same time when the victim net has a falling transition. The aggressor net switching in the opposite direction increases the delay for the victim. The positive crosstalk impacts the driving cell, as well as the net, interconnect - the delay for both gets increased because the charge required for the coupling capacitance Cc is more.

Negative crosstalk: the aggressor net is a rising transition at the same time as the victim net. The aggressor's net switching in the same direction decrease delay of the victim. The positive crosstalk impacts the driving cell, as well as the net, interconnect - the delay for both gets decreased because the charge required for the coupling capacitance Cc is less.

Crosstalk effect on timing analysis:

Consider crosstalk in data path:
If the aggressor transition in the same direction as the victim then victim transition becomes fast because of this data will be arrive early means arrival time will be less.
Setup = RT – AT(dec) this is good for setup #dec- decrease
Hold = AT(dec) – RT this is bad for hold

If the aggressor transition in a different direction as a victim then victim transition becomes slow because of this data will be arrive late means arrival time will be more.


Setup = RT – AT(inc) this is not good for setup
Hold = AT(inc) – RT this is good for hold #inc- increase

Consider crosstalk in the clock path:
If the aggressor transition in the same direction as the victim then victim transition becomes fast because of this clock will be arrive early means Required time will be less.

Setup = RT(dec) – AT this is not good for setup

Hold = AT – RT(dec) this is good for hold

If the aggressor transition in a different direction as a victim then victim transition becomes slow because of this clock will be arrive late means the Required time will be more.

Setup = RT(inc) – AT this is good for setup

Hold = AT – RT(inc) this is not good for hold

How to reduce the crosstalk:

• Wire spacing (NDR rules) by doing this we can reduce the coupling capacitance between two nets.
• Increased the drive strength of victim net and decrease the drive strength of aggressor net
• Jumping to higher layers (because higher layers have width is more)
• Insert buffer to split long nets
• Use multiple vias means less resistance then less RC delay
• Shielding: high-frequency noise is coupled to VSS or VDD since shielded layers are connects to either VDD or VSS. The coupling capacitance remains constant with VDD or VSS.

Clock Uncertainty

Clock Uncertainty : The Time difference between the arrival of the clock signal at the register in one clock domain or between any two clock domains


Uncertainty is caused by following factors:

• clock skew
• clock jitter
• cross talk

Clock Skew

• Skew is the difference in clock arrival time across the chip.
• Clock Skew is the temporal difference between the arrival of the same edge of a clock signal at the Clock pin of the capture and launch flops.
• Signal takes time to move from one location to another. Clock latency is the time taken by a clock signal to move from the clock source to the clock pin of a particular flip-flop. Clock skew can alternatively be defined as the difference between capture and launch flop delay.

For example, The capture clock delay is 2.5ns while the launch clock latency is 0ns. The difference between them is 2.5ns-0ns = 2.5ns, which is the clock skew value

The clock should ideally reach the clock pin of all the flip-flops in a design at the same time, resulting in a zero skew. However, this is not attainable owing to varying wire-interconnect lengths and temperature changes.

What is the reason for skew in a design?

A skew in a design occurs when a flip-flop is put near the clock source and another flip-flop is placed at the far end of the core region. In practice, the skew cannot be zero due to the disparity in connecting lengths. To address this, a user-specified number is provided to obtain correct pre-CTS timing data. After the clock tree is constructed, the real skew values are accessible, and the uncertainty is limited to the Jitter value alone.

The time difference/delta between the launch flip flop and capture flip flop or
it refers to the absolute time diff between the clock signal arrival between the two points in the clock network

Tskew =Tlaunch_clk - Tcapture_clk

skew can be classified into different skews:

•  +ve skew: Positive clock skew, In this case, the capture clock delay is greater than the launch clock latency. Positive skew is advantageous for setup timing. Due to the inclusion of skew, the capture clock is delayed by a few ns. Therefore the timing path requires one clock period and Skew margin to match the setup requirement.
• -ve skew: Negative Skew is beneficial for hold time since it delays the fresh launch. Because of the delay in launching the new data, the prior data will be effectively recorded and will not be overwritten. However, negative skew is detrimental to setup timing.
• Local skew: The disparity in latency between two related flops in a design is referred to as local skew.
• Global skew: is the difference in clock delay between two unrelated flops or the difference between the longest and shortest clock paths in the design.
• Usefull Skew :Useful skew is the skew that is purposefully introduced into the design to satisfy timing. It is particularly introduced in clock pathways where timing is failing, so that timing is passed in that path. However, useful skew cannot be applied arbitrarily. This must be done with caution, ensuring that the margin is accessible in both the preceding and subsequent time paths. The uncontrolled insertion of skew might result in further timing violations rather than resolving them. It may be used to correct both setups and hold errors 

Cock Jitter

It can be defined as “deviation of a clock edge from its ideal location.” Clock jitter is typically caused by clock generator circuitry, noise, power supply variations, interference from nearby circuitry etc. Jitter is a contributing factor to the design margin specified for timing closure.
Based on how it is measured in a system, jitter is of following types:
Period jitter
Period jitter is the deviation in cycle time of a clock signal with respect to the ideal period over a number of randomly selected cycles(say 10K cycles). It can be specified an average value of of clock period deviation over the selected cycles(RMS value) or can be the difference between maximum deviation & minimum deviation within the selected group(peak-to-peak period jitter).

Cycle to cycle jitter : 

C2C is the deviation in cycle of of two adjacent clock cycles over a random number of clock cycles. (say 10K). This is typically reported as a peak value within the random group.This is used to determine the high frequency jitter.
 

Phase jitter:

In frequency domain, the effect being measured is phase noise. It is the frequency domain representation of rapid, short-term, random fluctuations in the phase of a waveform. This can be translated to jitter values for use in digital design.

Please note all the above jitters are effectively the same phenomenon, but different way of measuring and representing the effect for use in design flow. The jitter number thus obtained is used to specify the design margin using the command “set_clock_uncertainty”.

Effects
Since the jitter affects the clock delay of the circuit and the time the clock is available at sync points, setup and hold of the path elements are affected by it. Depending on whether the jitter causes the clock to be slower or faster, there can be setup hold or setup violations in an otherwise timing clean system. This will in turn lead to performance or functional issues for the chip. So it is necessary that the designer knows the jitter values of the clock signal and need to be considered while analyzing timing.

Cross Talk

Swtiching of the signal in one net will effect the signal in neighboring net due to cross coupling capacitance, know as Cross Talk. This noise will affect the functionality of chip