A Vec in chisel represents a collections signal (same type). These are similar to the array data structures in other languages. Each element in Vec can be accessed by an index. A Vec will be created by calling a constructor with two parameters:
The number of elements
The type of the elements
The combinations vec must be wrap into a wire. val vs = Wire(Vec(3 , UInt(4.W)))
Individual elements of the vecot can be accessed by index vs(0) := 1.U vs(1) := 2.U vs(2) := 3.U
A vector wrapped into a Wire is multiplexer. We can also wrap the vec into register to define the array of registers as shown below val regfile = Reg(Vec(32, UInt(32.W)) The elements of that register are accessed by index val idx = 1.U(2.W) val dout = regfile(idx)
We can freely mix bundles and vectors, as shown below
val vecBundle = Wire(Vec(8, new vlsiscape() ) ) —> vlsispace() was a bundle defined
In Chisel provides two constructs to group related signals
A Bundle to group signals of different type.
A Vec represents the collection of signal of same type.
A chisel Bundle groups several signals. The entire bundle can be accessed or individual field can be accessed by their names. User or Designer can define a bundle(collections of signals) by definnig a class which extends Bundle and list the fields as vals within the constructor block
class vlsispace() extends Bundle { val vlsi = UInt(32.W) val space = Bool() }
To access the bundle in following way val vs = Wire(new vlsispace()) vs.vlsi := 124.U vs.space := false.B
val a = vs.space
By using the dot we can access the field of the particular constructor, which is commonly used in object oriented programming. A Bundle is similar to struct in C , a record in VHDL or struct in system verilog. A bundle can be referred as a whole as follows
val channel = vs
A bundle may as well contain a vector:
class BundleVec extends Bundle { val vs = UInt(8.U) val vector = Vec(4 , UInt(4,W)) }
When we want a register of a bundle type that needs a reset value, we first wire of that bundle and define the values for the bundle elements and then passing the bundle to RegInit:
val initval = Wire( new vlsispcae()) initval.vlsi := 1.U initval.space := true.B
By using full adder, a single 1-bit binary adders can be constructed from basic logic gates as shown below
But what if we wanted to add together two n-bit numbers, then n number of 1-bit full adders need to be connected or “cascaded” together to produce a adder known as a Ripple Carry Adder.
Ripple carry adder is simply “n“ number of 1-bit full adders cascaded together with full adder representing a single weighted column in a long binary addition. It is called a ripple carry adder because the carry signals produce a “ripple” effect through the binary adder from LSB to MSB.
Let us consider a three bit full adders to “add” together two 3-bit numbers, the two outputs of the first full adder will provide the first place digit sum (S) of the addition plus a carry-out bit that acts as the carry-in digit of the next binary adder. The second binary adder in the chain also produces a summed output (the 2nd bit) plus another carry-out bit and we can keep adding more full adders to the combination to add larger numbers, linking the carry bit output from the first full binary adder to the next full adder, and so forth. An example of a 3-bit adder is given below.
Let us consider A =4 , B=3, sum of A and B will be 7. In binary addition
There will be a overflow ,If the sum was greater than or equal to 2n one of the disadvantage in this adder. Let us consider A =4 , B=4, Sum of A and B will be 8 which is equal to 23 and we will have a overflow .
There two main disadvantages in ripple carry adder
Propagation delay: if inputs A and B changes, the sum at its output will not be valid until any carry-input has “rippled” through every full adder in the chain because the MSB of the sum has to wait for any changes from the carry input of the LSB. Consequently, there will be a finite delay before the output of the adder responds to any change in its inputs resulting in a accumulated/propagation delay. This delay can be neglected for 4 to 8 bits but we cannot neglect the delay for higher bits like 32 bits and more.
Over flow: Overflow occurs when the two n bit numbers add together whose sum is greater than or equal to 2n
To reduce the propagation delay of carry_in we can use Carry Look Ahead Binary Adder
In digital systems counter is plays a main role. Counters are used to keep a track of events , time intervals and no of interrupts etc. . Counter can be programmed in many languages like verilog, c , c++ , java, python, chisel etc. In this post we will see how to program a counter in chisel language.
Design a counter which starts counting from 0 till 9 and reset to 0 once it counts till 9.
val cntSpace = RegInit (0.U (8.U))—> defines a 8 bit register which initialize to 0 upon reset signal cntSpace := Mux( cntSpace ===9.U , 0.U, cntSpace + 1.U)
:= ——> update register When the cntSpace reaches to 9, it will initialize to 0 otherwise the cntSpace will be incremented by one
Scan cell is one of the DFT technique , to test the sequential circuits in the Asic/Soc design. Normal D flip flop are converted to scan flip flop, if the tool meets the following criteria
Clock of the flip flop must be controllable
The set/reset of the flops must be inactive during the shift mode.
Once the all the flops in the design meet the above two rules the tool will convert the d flops to scan flops by adding a mux as shown in figure above. Then the tools will stitch the scan cells into a scan chain according to the design requirements.
When Scan Enable is 0 (SE=0), all the scan chains in the design will be disconnected and the flops are connected to comb. logic
When Scan Enable is 1 (SE=1) , combinational logic will be bypassed and all scan cells will be connected to form a scan chain
When SE=1 , patterns are loaded to the scan chains and the data from the comb logic are captured when SE=0
Scan chain reordering is an optimization technique to ensure scan chains are connected in more efficient way – based upon the placement of the flip-flops. At initial stage , we donot have the placement information, so we just stitch the flops register by register. The tools will stitch the flops randomly to form a scan chain before placement. For proper understanding flops are numbered and two scan chains are stitched in the screen shot shown below.
But after placement it might be possible that the two flops stitched at initial stage of a different block sits far from each other when the placement is done. So if we keep the same scan chain order, we will face the placement congestion and timing congestion and more routing resources are required.
We can see from above screenshot, depending on the timing and placement congestion flops are placed at different locations when compared to before placement figure. This results in usage of more resources, space congestion increases and also timing violations. By reordering the scan cells in the scan chain we can reduce the congestion
In order to avoid the congestion before placement we have to follow the below steps
Disconnect the scan chain in the designing.
Based on the timing and congestion the tool optimizes the standard cells
Once the placement was done, reordering of scan chains are done based on the timing and placement congestion in design by maintaining the same number of scan cells .
SCANDEF file contains the scan chain information of the design and this file need to be read during PnR.
Faults list in design are categorized into sub categories. Faults class are mainly divided into
Testable(TE)–> Faults can be tested by some patterns.
Untestable(UT)–> Faults foe which no pattern exits to detect the faults
Untestable Faults: Are the faults for which no pattern exit to either detect or possible detect them. These faults cannot cause any functional failures. And so the tools excludes them while calculating the test coverage. Types of Untestable faults are
Unused (UU)
Tied (TI)
Blocked(BL)
Redundant Faults (RE)
Unused (UU)
Any floating pins not used in the design come under UU faults
The unused faults class includes all the faults on circuit unconnected to any observation point
Tied (TI)
This faults includes faults on gates where the point of the faults is tied to a value identical to the fault stuck value
Blocked (BL)
Due to tied logic in the design few faults are blocked and these are categories into Blocked faults. By adding the observable test point we can increase the coverage report.
Redundant (RE)
The faults which are undetectable by the tool by any pattern , are classified as redundant faults
