A Vec in chisel represents a collections signal (same type). These are similar to the array data structures in other languages. Each element in Vec
Tag: vlsi
CHISEL : Bundle
In Chisel provides two constructs to group related signals A Bundle to group signals of different type. A Vec represents the collection of signal of
n bit binary adder or ripple carry adder
By using full adder, a single 1-bit binary adders can be constructed from basic logic gates as shown below But what if we wanted to
CHISEL: Counter in Chisel
In digital systems counter is plays a main role. Counters are used to keep a track of events , time intervals and no of interrupts
scan cell, scan chain
Scan cell is one of the DFT technique , to test the sequential circuits in the Asic/Soc design. Normal D flip flop are converted to
scan chain REORDERING , why it is required
Scan chain reordering is an optimization technique to ensure scan chains are connected in more efficient way – based upon the placement of the flip-flops.
Untestable faults in DFT
Faults list in design are categorized into sub categories. Faults class are mainly divided into Testable(TE)–> Faults can be tested by some patterns. Untestable(UT)–> Faults
Fault Class Hierarchies in DFT
Faults list in design are categorized into sub categories. Faults class are mainly divided into Testable(TE)–> Faults can be tested by some patterns. Untestable(UT)–> Faults
Different ways of Digital design representation
A digital design can be represented at various levels from three different angles Behavioral Structural Physical This can be represented by Y chart Behavioral Representation