Dataflow modeling is a higher level of abstraction. The designer no need have any knowledge of logic circuit. He should be aware of data flow
Tag: vlsi
Gate level Modelling
The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design Gate primitives
Gate delays
Gate Delays In Verilog, a designer can specify the gate delays in verilog code. This helps the designer to get a real time behavior of
Basics : Data Types III
Vectors Vectors can be a net or reg data types. They are declared as [high:low] or [low:high], but the left number is always the MSB
Basics : Data types II
Integers Integer is a register data type of 32 bits. The only difference of declaring it as integer is that, it becomes a signed value.
Synchronous Reset and Asynchronous Reset
A Reset is required to initialize a hardware design for system operation and to force an value into a known state for simulation. A reset
CHISEL : Vec
A Vec in chisel represents a collections signal (same type). These are similar to the array data structures in other languages. Each element in Vec
CHISEL : Bundle
In Chisel provides two constructs to group related signals A Bundle to group signals of different type. A Vec represents the collection of signal of
n bit binary adder or ripple carry adder
By using full adder, a single 1-bit binary adders can be constructed from basic logic gates as shown below But what if we wanted to
CHISEL: Counter in Chisel
In digital systems counter is plays a main role. Counters are used to keep a track of events , time intervals and no of interrupts